Texas Instruments TMS320C6712D warranty SYNCHRONOUS-BURST Memory Timing, Unit MIN MAX

		SPRS293A − OCTOBER	2005 − REVISED NOVEMBER 2005
		SYNCHRONOUS-BURST MEMORY TIMING
timing requirements for synchronous-burst SRAM cycles† (see Figure 28)
NO.				−150		UNIT
				MIN	MAX
6	tsu(EDV-EKOH)	Setup time, read EDx valid before ECLKOUT high		1.5		ns
7	th(EKOH-EDV)	Hold time, read EDx valid after ECLKOUT high		2.5		ns

†The SBSRAM interface takes advantage of the internal burst counter in the SBSRAM. Accesses default to incrementing 4-word bursts, but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow.

switching characteristics over recommended operating conditions for synchronous-burst SRAM cycles†‡ (see Figure 28 and Figure 29)

NO.		PARAMETER						−150		UNIT
								MIN	MAX
1	td(EKOH-CEV)	Delay time, ECLKOUT high to			valid			1.2	7	ns
			CEx
2	td(EKOH-BEV)	Delay time, ECLKOUT high to			valid				7	ns
			BEx
3	td(EKOH-BEIV)	Delay time, ECLKOUT high to			invalid			1.2		ns
			BEx
4	td(EKOH-EAV)	Delay time, ECLKOUT high to EAx valid							7	ns
5	td(EKOH-EAIV)	Delay time, ECLKOUT high to EAx invalid						1.2		ns
8	td(EKOH-ADSV)	Delay time, ECLKOUT high to						1.2	7	ns
						ARE/SDCAS/SSADS valid
9	td(EKOH-OEV)	Delay time, ECLKOUT high to,						1.2	7	ns
							AOE/SDRAS/SSOE valid
10	td(EKOH-EDV)	Delay time, ECLKOUT high to		valid					7	ns
			EDx
11	td(EKOH-EDIV)	Delay time, ECLKOUT high to		invalid				1.2		ns
			EDx
12	td(EKOH-WEV)	Delay time, ECLKOUT high to						1.2	7	ns
			AWE/SDWE/SSWE valid

†The SBSRAM interface takes advantage of the internal burst counter in the SBSRAM. Accesses default to incrementing 4-word bursts, but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow.

‡ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses.

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