SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005

 

 

 

 

 

 

 

 

Terminal Functions

 

 

 

PIN

 

 

 

 

 

 

SIGNAL

NO.

TYPE

IPD/

 

 

DESCRIPTION

 

 

 

 

 

NAME

GDP/

IPU

 

 

 

 

 

 

 

 

 

 

ZDP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLOCK/PLL

 

 

 

 

 

 

 

 

CLKIN

A3

I

IPU

Clock Input

 

 

 

 

 

 

 

 

 

 

 

 

 

The CLKOUT2 pin is multiplexed with the GP[2] pin. Clock output at half of device speed (O/Z)

 

 

 

 

 

 

[default] (SYSCLK2 internal signal from the clock generator) or this pin can be programmed as

 

 

 

 

 

 

GP[2] (I/O/Z).

 

CLKOUT2

Y12

O/Z

IPD

When the CLKOUT2 pin is enabled, the CLK2EN bit in the EMIF global control

 

 

 

 

 

 

 

 

 

 

 

 

register (GBLCTL) controls the CLKOUT2 pin (All devices).

 

 

 

 

 

 

CLK2EN = 0: CLKOUT2 is disabled

 

 

 

 

 

 

CLK2EN = 1: CLKOUT2 enabled to clock [default]

 

 

 

 

 

 

 

 

CLKOUT3

D10

O

IPD

Clock output programmable by OSCDIV1 register in the PLL controller

 

 

 

 

 

 

 

 

 

 

 

 

 

Clock generator input clock source select

 

 

 

 

 

 

0

Reserved. Do not use.

 

CLKMODE0

C4

I

IPU

1

CLKIN square wave [default]

 

 

 

 

 

 

For proper device operation, this pin must be either left unconnected or

 

 

 

 

 

 

externally pulled up with a 1-kresistor.

 

 

 

 

 

 

 

 

PLLHV

C5

A

 

Analog power (3.3 V) for PLL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

JTAG EMULATION

 

 

 

 

 

 

 

 

TMS

B7

I

IPU

JTAG test-port mode select

 

 

 

 

 

 

 

 

TDO

A8

O/Z

IPU

JTAG test-port data out

 

 

 

 

 

 

 

 

TDI

A7

I

IPU

JTAG test-port data in

 

 

 

 

 

 

 

 

TCK

A6

I

IPU

JTAG test-port clock

 

 

 

 

 

 

 

 

 

 

 

 

 

JTAG test-port reset. For IEEE 1149.1 JTAG compatibility, see the IEEE 1149.1

 

TRST§

B6

I

IPD

 

JTAG Compatibility Statement section of this data sheet.

 

 

 

 

 

 

 

 

 

 

 

 

 

EMU5

B12

I/O/Z

IPU

Emulation pin 5. Reserved for future use, leave unconnected.

 

 

 

 

 

 

 

EMU4

C11

I/O/Z

IPU

Emulation pin 4. Reserved for future use, leave unconnected.

 

 

 

 

 

 

 

EMU3

B10

I/O/Z

IPU

Emulation pin 3. Reserved for future use, leave unconnected.

 

 

 

 

 

 

 

EMU2

D3

I/O/Z

IPU

Emulation pin 2. Reserved for future use, leave unconnected.

I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal (PLL Filter)

IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors no greater than 4.4 kand 2.0 k, respectively.]

§To ensure a proper logic level during reset when these pins are both routed out and 3-stated or not driven, it is recommended that an external 10-kpullup/pulldown resistor be included to sustain the IPU/IPD, respectively.

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Texas Instruments TMS320C6712D warranty Terminal Functions, PIN Signal, IPD Description Name GDP IPU‡ ZDP

TMS320C6712D specifications

The Texas Instruments TMS320C6712D is a high-performance, fixed-point digital signal processor (DSP) that belongs to the TMS320C6000 family, well known for its advanced processing capabilities tailored for demanding signal processing applications. Launched in the early 2000s, the C6712D combines high computational power with a rich set of features, making it suitable for a variety of applications such as telecommunications, audio processing, and industrial control systems.

One of the standout characteristics of the TMS320C6712D is its architecture, which is based on a highly efficient VLIW (Very Long Instruction Word) design. This architecture allows the processor to execute multiple instructions in a single clock cycle, significantly increasing performance. The device operates at clock speeds of up to 150 MHz, providing substantial computational throughput that can handle complex algorithms and real-time processing tasks.

Another key feature of the TMS320C6712D is its 32-bit fixed-point processing capabilities, which allows it to perform difficult mathematical computations efficiently. With an instruction set optimized for DSP applications, the processor includes specialized instructions for multiplying and accumulating operations, as well as support for advanced filtering and generation of audio signals.

The C6712D offers an extensive memory architecture, supporting up to 128 MB of external memory via a 32-bit data bus. It features on-chip SRAM, which provides fast access to data and program storage, enhancing the system's overall performance. Additionally, the device includes a powerful set of peripherals, such as dual asynchronous serial ports (UART), I2C interfaces, and DSP-specific interfaces that facilitate connectivity with other components and systems.

Power consumption is another vital aspect of the TMS320C6712D. It incorporates technologies allowing for low-power operation, which is essential for portable and battery-operated devices. The capability to operate in various power modes helps optimize performance while minimizing energy usage.

In conclusion, the Texas Instruments TMS320C6712D is a versatile and powerful DSP that excels in high-performance applications. Its VLIW architecture, fixed-point processing capabilities, extensive memory options, and low power consumption make it an ideal choice for engineers looking to implement complex signal processing tasks efficiently. Whether used in telecommunications, audio processing, or industrial applications, the C6712D remains a reliable and capable solution in the digital signal processing landscape.