Signal Name PIN GDP ZDP TYPE† | Texas Instruments TMS320C6712D

Terminal Functions (Continued)

DESCRIPTION

GROUND PINS (CONTINUED)

SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005

SIGNAL

NAME

NO.

GDP/

ZDP

TYPE†

	D17

	E2

	E4

	E17

	F19

	G4

	G17

	H4

	H17

	J4

	J9
	J10
	J11
	J12
	K2

	K9
	K10
	K11
	K12		Ground pins
	K20		Ground pins
VSS	K20	GND	The center thermal balls (J9−J12, K9−K12, L9−L12, M9−M12) [shaded] are all tied to ground and act as

	L9
	L9		both electrical grounds and thermal relief (thermal dissipation).
	L10
	L11
	L12
	M4

	M9
	M10
	M11
	M12
	M17

	N4

	N17

	P4

	P17

	P19

	T4

	T17

	U4

	U8

	U9

†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal (PLL Filter) Shaded pin numbers denote the center thermal balls for the GDP and ZDP packages.

34	POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

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Texas Instruments TMS320C6712D warranty Signal Name PIN GDP ZDP TYPE†, Vss Gnd

TMS320C6712D specifications

The Texas Instruments TMS320C6712D is a high-performance, fixed-point digital signal processor (DSP) that belongs to the TMS320C6000 family, well known for its advanced processing capabilities tailored for demanding signal processing applications. Launched in the early 2000s, the C6712D combines high computational power with a rich set of features, making it suitable for a variety of applications such as telecommunications, audio processing, and industrial control systems.

One of the standout characteristics of the TMS320C6712D is its architecture, which is based on a highly efficient VLIW (Very Long Instruction Word) design. This architecture allows the processor to execute multiple instructions in a single clock cycle, significantly increasing performance. The device operates at clock speeds of up to 150 MHz, providing substantial computational throughput that can handle complex algorithms and real-time processing tasks.

Another key feature of the TMS320C6712D is its 32-bit fixed-point processing capabilities, which allows it to perform difficult mathematical computations efficiently. With an instruction set optimized for DSP applications, the processor includes specialized instructions for multiplying and accumulating operations, as well as support for advanced filtering and generation of audio signals.

The C6712D offers an extensive memory architecture, supporting up to 128 MB of external memory via a 32-bit data bus. It features on-chip SRAM, which provides fast access to data and program storage, enhancing the system's overall performance. Additionally, the device includes a powerful set of peripherals, such as dual asynchronous serial ports (UART), I2C interfaces, and DSP-specific interfaces that facilitate connectivity with other components and systems.

Power consumption is another vital aspect of the TMS320C6712D. It incorporates technologies allowing for low-power operation, which is essential for portable and battery-operated devices. The capability to operate in various power modes helps optimize performance while minimizing energy usage.

In conclusion, the Texas Instruments TMS320C6712D is a versatile and powerful DSP that excels in high-performance applications. Its VLIW architecture, fixed-point processing capabilities, extensive memory options, and low power consumption make it an ideal choice for engineers looking to implement complex signal processing tasks efficiently. Whether used in telecommunications, audio processing, or industrial applications, the C6712D remains a reliable and capable solution in the digital signal processing landscape.

Contents

SPRS293A − October 2005 − Revised November Table of Contents Revision History Pages ADDITIONS/CHANGES/DELETIONS Multichannel Buffered Serial Port Timing GDP and ZDP 272-PIN Ball Grid Array BGA Package GDP and ZDP BGA package bottom viewBottom View Description Hardware Features Internal Clock Device characteristicsCharacteristics of the C6712D Processor C6712D Device compatibility Functional block and CPU DSP core diagram Digital Signal Processor CPU DSP core description DA2 ST1DA1 ST2 Memory Map Summary Memory map summaryMemory Block Description Block Size Bytes HEX Address Range L2 Cache Registers Peripheral register descriptionsEmif Registers HEX Address Range Acronym Register Name Edma Parameter RAM† Interrupt Selector RegistersDevice Registers HEX Address Range Acronym Register Name Comments Edma Registers Quick DMA Qdma and Pseudo Registers† PLL Controller Registers Gpio Registers HEX Address Range Acronym Register Name Comments Timer McBSP0 and McBSP1 Registers Jtag Signal groups descriptionClkin CLKOUT3 CLKOUT2† CLKMODE0 Pllhv TMS TDO TDI TCK Trst BIG/LITTLE Endian CLKS1† TOUT1 TINP1CLKR1 Gpio Device Configurations Device configurations at device reset Emifbe Configuration GDP/ZDP Functional Description PINBOOTMODE10 Lendian Eksrc Devcfg register descriptionBIT # Name Description Terminal Functions Terminal Functions PIN SignalIPD Description Name GDP IPU‡ ZDP EMU1B9 EMU0D9 IPU BootmodeBOOTMODE1 C19 BOOTMODE0 C20 IPD LITTLE/BIG Endian Format Edge-driven IPD Description Name GDP IPU‡ ZDP Resets and InterruptsOnly one asserted during any external data access Decoded from the two lowest bits of the internal address Emif − Address # Emif − Data # IPD Description Name GDP IPU‡ ZDP Emif − Data # TIMER1TIMER0 Multichannel Buffered Serial Port 1 McBSP1 GENERAL-PURPOSE INPUT/OUTPUT Gpio Module Multichannel Buffered Serial Port 0 McBSP0Reserved for Test RSV IPD IPD Description Name GDP IPU ZDPRSV IPU Additional Reserved for Test SPRS293A − October 2005 − Revised November Dvdd Name GDP ZDP Supply Voltage PinsSee the power-supply decoupling portion of this data sheet Cvdd VSS Description Name GDP ZDP Supply Voltage PinsGround Pins GND Signal Name PIN GDP ZDP TYPE† VSS GND Description GDP Name ZDP Ground Pins VSS Software Development Tools Development supportHardware Development Tools Device and development-support tool nomenclature Device supportFully qualified production device Device Family Temperature Range Default 0C to 90CPrefix Technology Documentation support Pwrd CPU CSR register descriptionRevision ID PCC DCC Pgie GIE CPU ID CPU CSR Register Bit Field DescriptionPCC Ccfg Register Bit Field Description Cache configuration Ccfg register descriptionL2MODE DSP Interrupts Interrupt Selector DSP Interrupt Default Selector Module ControlInterrupt sources and interrupt selector Event Edma Channels Edma module and Edma selectorEdma Selector ESEL1 Register 0x01A0 FF04 ESEL3 Register 0x01A0 FF0C PLL and PLL controller Enabled or Disabled PLL Lock and Reset TimesClkout Signals, Default Settings, and Control MIN TYP MAX Unit PLL Clock Frequency Ranges†‡ Clock SignalGDP 150and ZDP Pllcsr Register 0x01B7 C100 PLL Control/Status Register Pllcsr Pllm Register 0x01B7 C110 PLL Multiplier Control Register Pllm DxEN Oscillator Divider 1 Register OSCDIV1 OSCDIV1 Register 0x01B7 C124OD1EN GP7 GP6 GP5 GP4 GP2 General-purpose input/output GpioDIR Power-down mode logic Pwrd Field of the CSR Register PD3 PD2 PD1 Power-supply design considerations Power-supply sequencingCharacteristics of the Power-Down Modes System-level design considerations GND Dvdd Power-supply decouplingSupply Schottky Diode Core Supply C6000 Ieee 1149.1 Jtag compatibility statement Emif device speed Example Boards and Maximum Emif Speed Reset Emif big endian mode correctnessBootmode Emif Data Lines Pins Where Data Present MIN NOM MAX Unit Recommended operating conditionsIOH Parameter Test Conditions MIN TYP MAX Unit IOZ 42 Ω Signal transition levelsParameter Measurement Information Vref = 1.5 AC transient rise/fall time specifications = 0.3 tcmax† VIL max VUS max Ground Timing parameters and board routing analysis Board-Level Timings Example see Figure Control Signals † Output from DSPOutput from DSP Timing requirements for CLKIN†‡§ Input and Output ClocksSee Figure Timing requirements for ECLKIN§ see Figure Clkin CLKOUT3 MIN Eclkin Eclkout See −Figure Asynchronous Memory TimingTiming requirements for asynchronous memory cycles†‡ Are ED150 Read Data Setup = Strobe = Not Ready Hold =CE30 BE10 EA212 AOE/SDRAS/SSOE† ARE/SDCAS/SSADS† AWE/SDWE/SSWE† Ardy ED310 CEx BE30 EA212AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE † Ardy SYNCHRONOUS-BURST Memory Timing Unit MIN MAX EA212 ED150 CE30 BE10BE1 BE2 BE3 BE4 ARE/SDCAS/SSADS † AOE/SDRAS/SSOE † AWE/SDWE/SSWE† Timing requirements for synchronous Dram cycles† see Figure Synchronous Dram Timing150 EA2113 Bank EA112 Column EA12 ED150 Read EclkoutAOE/SDRAS/SSOE † ARE/SDCAS/SSADS† AWE/SDWE/SSWE† EA12 ED150 Write EclkoutEA2113 AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE † AOE/SDRAS/SSOE† ARE/SDCAS/SSADS† AWE/SDWE/SSWE† Actv EclkoutCE30 BE10 EA2113 Bank Activate EA112 Row Address EA12 ED150 Dcab Eclkout EA112 EA12 ED150 Deac EclkoutCE30 BE10 EA2113 Refr Eclkout MRS Eclkout CE30 BE10 EA212 MRS value ED150 Hold HOLD/HOLDA TimingTiming requirements for the HOLD/HOLDA cycles† see Figure Hold Holda Busreq Timing Eclkout Busreq Timing requirements for reset†‡ see Figure Reset TimingCLKMODE0 = Phase Emif Z Group † Emif Low Group † Boot and Device Timing requirements for external interrupts† see Figure External Interrupt TimingEXTINT, NMI Multichannel Buffered Serial Port Timing Timing requirements for McBSP†‡ see Figure Parameter Bitn-1 Clks ClkrFSR int Clkx FSR external CLKR/X no need to resync CLKR/X needs resync Timing requirements for FSR when Gsync = 1 see FigureClks Master Slave Unit MIN MAX Clkx FSX Parameter MASTER§ Slave Unit MIN MAXBit Bitn-1 McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = Multichannel Buffered Serial Port Timing McBSP Timing as SPI Master or Slave Clkstp = 10b, Clkxp = McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = Timing requirements for timer inputs† Timer TimingTINPx TOUTx Timing requirements for Gpio inputs†‡ GENERAL-PURPOSE INPUT/OUTPUT Gpio Port TimingGPIx GPOx Timing requirements for Jtag test port see Figure Jtag TEST-PORT TimingUnit MIN MAX TCK TDO TDI/TMS/TRST Thermal resistance characteristics S-PBGA package for ZDP Package thermal resistance characteristicsThermal resistance characteristics S-PBGA package for GDP Mechanical Data MSL Peak Temp Orderable Device Status Package Pins Package Eco PlanPackaging Information Qty GDP S-PBGA-N272 Seating Plane 4204396/A 04/02 ZDP S-PBGA-N272 Seating Plane 4204398/A 04/02 Important Notice