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Texas Instruments TMS320C6712D Timing requirements for FSR when Gsync = 1 see Figure, Clks

Models: TMS320C6712D

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SPRS293 − OCTOBER 2005

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)

timing requirements for FSR when GSYNC = 1 (see Figure 42)

NO.					−150		UNIT

					MIN	MAX
					MIN	MAX

1	tsu(FRH-CKSH)	Setup time, FSR high before CLKS high			4		ns
2	th(CKSH-FRH)	Hold time, FSR high after CLKS high			4		ns
		CLKS
			1	2
			1

FSR external

CLKR/X (no need to resync)

CLKR/X (needs resync)

Figure 42. FSR Timing When GSYNC = 1

timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0†‡ (see Figure 43)

				−150

NO.			MASTER		SLAVE		UNIT
			MIN MAX		MIN	MAX

4	tsu(DRV-CKXL)	Setup time, DR valid before CLKX low	12		2 − 6P		ns
5	th(CKXL-DRV)	Hold time, DR valid after CLKX low	4		5 + 12P		ns

†P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns.

‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

Page 89

Image 89

Texas Instruments TMS320C6712D Timing requirements for FSR when Gsync = 1 see Figure, Clks, Master Slave Unit MIN MAX

Contents

SPRS293A − October 2005 − Revised November Table of Contents Pages ADDITIONS/CHANGES/DELETIONS Revision HistoryMultichannel Buffered Serial Port Timing Bottom View GDP and ZDP BGA package bottom viewGDP and ZDP 272-PIN Ball Grid Array BGA Package Description Characteristics of the C6712D Processor Device characteristicsHardware Features Internal Clock C6712DDevice compatibility Digital Signal Processor Functional block and CPU DSP core diagramCPU DSP core description DA1 ST1DA2 ST2Memory Block Description Block Size Bytes HEX Address Range Memory map summaryMemory Map Summary Emif Registers Peripheral register descriptionsL2 Cache Registers HEX Address Range Acronym Register NameDevice Registers Interrupt Selector RegistersEdma Parameter RAM† HEX Address Range Acronym Register Name CommentsQuick DMA Qdma and Pseudo Registers† Edma RegistersGpio Registers PLL Controller RegistersMcBSP0 and McBSP1 Registers HEX Address Range Acronym Register Name Comments TimerClkin CLKOUT3 CLKOUT2† CLKMODE0 Pllhv TMS TDO TDI TCK Trst Signal groups descriptionJtag BIG/LITTLE EndianCLKR1 TOUT1 TINP1CLKS1† GpioDevice configurations at device reset Device ConfigurationsBOOTMODE10 Configuration GDP/ZDP Functional Description PINEmifbe LendianBIT # Name Description Devcfg register descriptionEksrc Terminal Functions IPD Description Name GDP IPU‡ ZDP PIN SignalTerminal Functions BOOTMODE1 C19 BOOTMODE0 C20 IPD BootmodeEMU1B9 EMU0D9 IPU LITTLE/BIG Endian FormatOnly one asserted during any external data access IPD Description Name GDP IPU‡ ZDP Resets and InterruptsEdge-driven Decoded from the two lowest bits of the internal addressEmif − Data # Emif − Address #TIMER0 TIMER1IPD Description Name GDP IPU‡ ZDP Emif − Data # Multichannel Buffered Serial Port 1 McBSP1Reserved for Test Multichannel Buffered Serial Port 0 McBSP0GENERAL-PURPOSE INPUT/OUTPUT Gpio Module RSV IPU IPD Description Name GDP IPU ZDPRSV IPD Additional Reserved for TestSPRS293A − October 2005 − Revised November See the power-supply decoupling portion of this data sheet Name GDP ZDP Supply Voltage PinsDvdd CvddGround Pins Description Name GDP ZDP Supply Voltage PinsVSS GNDVSS GND Signal Name PIN GDP ZDP TYPE†VSS Description GDP Name ZDP Ground PinsHardware Development Tools Development supportSoftware Development Tools Fully qualified production device Device supportDevice and development-support tool nomenclature Prefix Temperature Range Default 0C to 90CDevice Family TechnologyDocumentation support Revision ID CPU CSR register descriptionPwrd PCC DCC Pgie GIEPCC CPU CSR Register Bit Field DescriptionCPU ID L2MODE Cache configuration Ccfg register descriptionCcfg Register Bit Field Description Interrupt sources and interrupt selector DSP Interrupt Default Selector Module ControlDSP Interrupts Interrupt Selector EventEdma Selector Edma module and Edma selectorEdma Channels ESEL3 Register 0x01A0 FF0C ESEL1 Register 0x01A0 FF04PLL and PLL controller Clkout Signals, Default Settings, and Control PLL Lock and Reset TimesEnabled or Disabled MIN TYP MAX UnitGDP 150and ZDP Clock SignalPLL Clock Frequency Ranges†‡ PLL Control/Status Register Pllcsr Pllcsr Register 0x01B7 C100PLL Multiplier Control Register Pllm Pllm Register 0x01B7 C110DxEN OD1EN OSCDIV1 Register 0x01B7 C124Oscillator Divider 1 Register OSCDIV1 DIR General-purpose input/output GpioGP7 GP6 GP5 GP4 GP2 Power-down mode logic PD3 PD2 PD1 Pwrd Field of the CSR RegisterCharacteristics of the Power-Down Modes Power-supply sequencingPower-supply design considerations System-level design considerationsSupply Schottky Diode Core Supply Power-supply decouplingGND Dvdd C6000Ieee 1149.1 Jtag compatibility statement Example Boards and Maximum Emif Speed Emif device speedBootmode Emif big endian mode correctnessReset Emif Data Lines Pins Where Data PresentIOH Recommended operating conditionsMIN NOM MAX Unit IOZ Parameter Test Conditions MIN TYP MAX UnitParameter Measurement Information Signal transition levels42 Ω Vref = 1.5= 0.3 tcmax† VIL max VUS max Ground AC transient rise/fall time specificationsTiming parameters and board routing analysis Output from DSP Control Signals † Output from DSPBoard-Level Timings Example see Figure See Figure Input and Output ClocksTiming requirements for CLKIN†‡§ Clkin CLKOUT3 Timing requirements for ECLKIN§ see FigureEclkin Eclkout MINTiming requirements for asynchronous memory cycles†‡ Asynchronous Memory TimingSee −Figure AreCE30 BE10 EA212 Setup = Strobe = Not Ready Hold =ED150 Read Data AOE/SDRAS/SSOE† ARE/SDCAS/SSADS† AWE/SDWE/SSWE† ArdyAOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE † Ardy CEx BE30 EA212ED310 Unit MIN MAX SYNCHRONOUS-BURST Memory TimingBE1 BE2 BE3 BE4 CE30 BE10EA212 ED150 ARE/SDCAS/SSADS † AOE/SDRAS/SSOE † AWE/SDWE/SSWE†150 Synchronous Dram TimingTiming requirements for synchronous Dram cycles† see Figure AOE/SDRAS/SSOE † ARE/SDCAS/SSADS† AWE/SDWE/SSWE† Read EclkoutEA2113 Bank EA112 Column EA12 ED150 EA2113 Write EclkoutEA12 ED150 AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE †CE30 BE10 EA2113 Bank Activate EA112 Row Address EA12 ED150 Actv EclkoutAOE/SDRAS/SSOE† ARE/SDCAS/SSADS† AWE/SDWE/SSWE† Dcab EclkoutCE30 BE10 EA2113 Deac EclkoutEA112 EA12 ED150 Refr EclkoutCE30 BE10 EA212 MRS value ED150 MRS EclkoutTiming requirements for the HOLD/HOLDA cycles† see Figure HOLD/HOLDA TimingHold Hold HoldaEclkout Busreq Busreq TimingCLKMODE0 = Reset TimingTiming requirements for reset†‡ see Figure Emif Z Group † Emif Low Group † Boot and Device PhaseEXTINT, NMI External Interrupt TimingTiming requirements for external interrupts† see Figure Timing requirements for McBSP†‡ see Figure Multichannel Buffered Serial Port TimingParameter FSR int Clks ClkrBitn-1 ClkxClks Timing requirements for FSR when Gsync = 1 see FigureFSR external CLKR/X no need to resync CLKR/X needs resync Master Slave Unit MIN MAXBit Bitn-1 Parameter MASTER§ Slave Unit MIN MAXClkx FSX McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = Multichannel Buffered Serial Port Timing McBSP Timing as SPI Master or Slave Clkstp = 10b, Clkxp = McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = TINPx TOUTx Timer TimingTiming requirements for timer inputs† GPIx GPOx GENERAL-PURPOSE INPUT/OUTPUT Gpio Port TimingTiming requirements for Gpio inputs†‡ Unit MIN MAX TCK TDO TDI/TMS/TRST Jtag TEST-PORT TimingTiming requirements for Jtag test port see Figure Thermal resistance characteristics S-PBGA package for GDP Package thermal resistance characteristicsThermal resistance characteristics S-PBGA package for ZDP Mechanical DataPackaging Information Orderable Device Status Package Pins Package Eco PlanMSL Peak Temp QtySeating Plane 4204396/A 04/02 GDP S-PBGA-N272Seating Plane 4204398/A 04/02 ZDP S-PBGA-N272Important Notice

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)

timing requirements for FSR when GSYNC = 1 (see Figure 42)

MIN

CLKS

FSR external

CLKR/X (no need to resync)

CLKR/X (needs resync)

Figure 42. FSR Timing When GSYNC = 1

MASTER

SLAVE

UNIT

MIN MAX