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| SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 |
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| Terminal Functions (Continued) |
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| SIGNAL | NO. | TYPE† | IPD/ | DESCRIPTION |
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| NAME | GDP/ | IPU‡ |
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| ZDP |
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| EMIF − | ASYNCHRONOUS/SYNCHRONOUS DRAM/SYNCHRONOUS BURST SRAM MEMORY CONTROL (CONTINUED) # |
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| ARE/SDCAS/ | V11 | O/Z | IPU | Asynchronous memory read enable/SDRAM |
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| SSADS |
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| AOE/SDRAS/ | W10 | O/Z | IPU | Asynchronous memory output enable/SDRAM |
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| SSOE |
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| AWE/SDWE/ | V12 | O/Z | IPU | Asynchronous memory write enable/SDRAM write enable/SBSRAM write enable |
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| ARDY | Y5 | I | IPU | Asynchronous memory ready input |
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| EMIF − ADDRESS # |
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| EA21 | U18 |
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| EA20 | Y18 |
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| EA19 | W17 |
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| EA18 | Y16 |
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| EA17 | V16 |
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| EA16 | Y15 |
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| EA15 | W15 |
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| EA14 | Y14 |
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| EMIF external address |
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| EA13 | W14 |
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| Note: EMIF address numbering for the device start with EA2 to maintain signal name compati- |
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| EA12 | V14 |
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| O/Z | IPU | bility with other C671x devices (e.g., C6711, C6713) [see the 16−bit EMIF addressing scheme in |
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| EA11 | W13 | the TMS320C6000 DSP External Memory Interface (EMIF) Reference Guide (literature num- |
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| ber SPRU266)]. |
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| EA10 | V10 |
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| EA9 | Y9 |
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| EA8 | V9 |
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| EA7 | Y8 |
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| EA6 | W8 |
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| EA5 | V8 |
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| EA4 | W7 |
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| EA3 | V7 |
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| EA2 | Y6 |
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| EMIF − DATA # |
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| ED15 | T19 |
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| ED14 | T20 |
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| ED13 | T18 | I/O/Z | IPU | External data |
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| ED12 | R20 |
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| ED11 | R19 |
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| ED10 | P20 |
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†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal (PLL Filter)
‡IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors no greater than 4.4 kΩ and 2.0 kΩ, respectively.]
#To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 | 27 |