SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Terminal Functions (Continued)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PIN

 

 

 

 

 

SIGNAL

NO.

TYPE

IPD/

DESCRIPTION

 

 

 

 

 

NAME

GDP/

IPU

 

 

 

 

 

 

 

 

 

 

 

 

 

ZDP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EMIF −

ASYNCHRONOUS/SYNCHRONOUS DRAM/SYNCHRONOUS BURST SRAM MEMORY CONTROL (CONTINUED) #

 

 

ARE/SDCAS/

V11

O/Z

IPU

Asynchronous memory read enable/SDRAM column-address strobe/SBSRAM address strobe

 

 

SSADS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AOE/SDRAS/

W10

O/Z

IPU

Asynchronous memory output enable/SDRAM row-address strobe/SBSRAM output enable

 

 

SSOE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AWE/SDWE/

V12

O/Z

IPU

Asynchronous memory write enable/SDRAM write enable/SBSRAM write enable

 

 

SSWE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ARDY

Y5

I

IPU

Asynchronous memory ready input

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EMIF − ADDRESS #

 

 

EA21

U18

 

 

 

 

 

 

 

 

 

 

 

 

EA20

Y18

 

 

 

 

 

 

 

 

 

 

 

 

EA19

W17

 

 

 

 

 

 

 

 

 

 

 

 

EA18

Y16

 

 

 

 

 

 

 

 

 

 

 

 

EA17

V16

 

 

 

 

 

 

 

 

 

 

 

 

EA16

Y15

 

 

 

 

 

 

 

 

 

 

 

 

EA15

W15

 

 

 

 

 

 

 

 

 

 

 

 

EA14

Y14

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EMIF external address

 

 

EA13

W14

 

 

 

 

 

 

Note: EMIF address numbering for the device start with EA2 to maintain signal name compati-

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EA12

V14

 

 

 

 

O/Z

IPU

bility with other C671x devices (e.g., C6711, C6713) [see the 16−bit EMIF addressing scheme in

 

 

 

 

 

 

 

 

 

 

 

 

EA11

W13

the TMS320C6000 DSP External Memory Interface (EMIF) Reference Guide (literature num-

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ber SPRU266)].

 

 

EA10

V10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EA9

Y9

 

 

 

 

 

 

 

 

 

 

 

 

EA8

V9

 

 

 

 

 

 

 

 

 

 

 

 

EA7

Y8

 

 

 

 

 

 

 

 

 

 

 

 

EA6

W8

 

 

 

 

 

 

 

 

 

 

 

 

EA5

V8

 

 

 

 

 

 

 

 

 

 

 

 

EA4

W7

 

 

 

 

 

 

 

 

 

 

 

 

EA3

V7

 

 

 

 

 

 

 

 

 

 

 

 

EA2

Y6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EMIF − DATA #

 

 

ED15

T19

 

 

 

 

 

 

 

 

 

 

 

 

ED14

T20

 

 

 

 

 

 

 

 

 

 

 

 

ED13

T18

I/O/Z

IPU

External data

 

 

 

 

 

 

 

 

 

 

 

 

ED12

R20

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ED11

R19

 

 

 

 

 

 

 

 

 

 

 

 

ED10

P20

 

 

 

 

I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal (PLL Filter)

IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors no greater than 4.4 kand 2.0 k, respectively.]

#To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.

POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443

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Image 27
Texas Instruments TMS320C6712D warranty Emif − Address #, Emif − Data #

TMS320C6712D specifications

The Texas Instruments TMS320C6712D is a high-performance, fixed-point digital signal processor (DSP) that belongs to the TMS320C6000 family, well known for its advanced processing capabilities tailored for demanding signal processing applications. Launched in the early 2000s, the C6712D combines high computational power with a rich set of features, making it suitable for a variety of applications such as telecommunications, audio processing, and industrial control systems.

One of the standout characteristics of the TMS320C6712D is its architecture, which is based on a highly efficient VLIW (Very Long Instruction Word) design. This architecture allows the processor to execute multiple instructions in a single clock cycle, significantly increasing performance. The device operates at clock speeds of up to 150 MHz, providing substantial computational throughput that can handle complex algorithms and real-time processing tasks.

Another key feature of the TMS320C6712D is its 32-bit fixed-point processing capabilities, which allows it to perform difficult mathematical computations efficiently. With an instruction set optimized for DSP applications, the processor includes specialized instructions for multiplying and accumulating operations, as well as support for advanced filtering and generation of audio signals.

The C6712D offers an extensive memory architecture, supporting up to 128 MB of external memory via a 32-bit data bus. It features on-chip SRAM, which provides fast access to data and program storage, enhancing the system's overall performance. Additionally, the device includes a powerful set of peripherals, such as dual asynchronous serial ports (UART), I2C interfaces, and DSP-specific interfaces that facilitate connectivity with other components and systems.

Power consumption is another vital aspect of the TMS320C6712D. It incorporates technologies allowing for low-power operation, which is essential for portable and battery-operated devices. The capability to operate in various power modes helps optimize performance while minimizing energy usage.

In conclusion, the Texas Instruments TMS320C6712D is a versatile and powerful DSP that excels in high-performance applications. Its VLIW architecture, fixed-point processing capabilities, extensive memory options, and low power consumption make it an ideal choice for engineers looking to implement complex signal processing tasks efficiently. Whether used in telecommunications, audio processing, or industrial applications, the C6712D remains a reliable and capable solution in the digital signal processing landscape.