Texas Instruments TMS320C6712D instruction

SPRS293 − OCTOBER 2005

MULTICHANNEL BUFFERED SERIAL PORT TIMING

timing requirements for McBSP†‡ (see Figure 41)

NO.					−150			UNIT

					MIN		MAX
					MIN		MAX

2	tc(CKRX)	Cycle time, CLKR/X	CLKR/X ext		2P§			ns
3	t	Pulse duration, CLKR/X high or CLKR/X low	CLKR/X ext	0.5 *t		−1 ¶		ns
	w(CKRX)			c(CKRX)
5	tsu(FRH-CKRL)	Setup time, external FSR high before CLKR low	CLKR int			9		ns

			CLKR ext			1
			CLKR ext			1

6	th(CKRL-FRH)	Hold time, external FSR high after CLKR low	CLKR int			6		ns

			CLKR ext			3
			CLKR ext			3

7	tsu(DRV-CKRL)	Setup time, DR valid before CLKR low	CLKR int			8		ns

			CLKR ext			0
			CLKR ext			0

8	th(CKRL-DRV)	Hold time, DR valid after CLKR low	CLKR int			3		ns

			CLKR ext			4
			CLKR ext			4

10	tsu(FXH-CKXL)	Setup time, external FSX high before CLKX low	CLKX int			9		ns

			CLKX ext			1
			CLKX ext			1

11	th(CKXL-FXH)	Hold time, external FSX high after CLKX low	CLKX int			6		ns

			CLKX ext			3
			CLKX ext			3

†CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.

‡P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns.

§The minimum CLKR/X period is twice the CPU cycle time (2P) and not faster than 75 Mbps (13.3 ns). This means that the maximum bit rate for communications between the McBSP and other device is 75 Mbps for 150 MHz CPU clock; where the McBSP is either the master or the slave. Care must be taken to ensure that the AC timings specified in this data sheet are met. The maximum bit rate for McBSP-to-McBSP communications is 67 Mbps; therefore, the minimum CLKR/X clock cycle is either twice the CPU cycle time (2P), or 15 ns (67 MHz), whichever

value is larger. For example, when running parts at 150 MHz (P = 6.7 ns), use 15 ns as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running parts at 60 MHz (P = 16.67 ns), use 2P = 33 ns (30 MHz) as the minimum CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP communications applies when the serial port is a master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX, CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP communicates to is a slave.

¶This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.

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TMS320C6712D specifications

The Texas Instruments TMS320C6712D is a high-performance, fixed-point digital signal processor (DSP) that belongs to the TMS320C6000 family, well known for its advanced processing capabilities tailored for demanding signal processing applications. Launched in the early 2000s, the C6712D combines high computational power with a rich set of features, making it suitable for a variety of applications such as telecommunications, audio processing, and industrial control systems.

One of the standout characteristics of the TMS320C6712D is its architecture, which is based on a highly efficient VLIW (Very Long Instruction Word) design. This architecture allows the processor to execute multiple instructions in a single clock cycle, significantly increasing performance. The device operates at clock speeds of up to 150 MHz, providing substantial computational throughput that can handle complex algorithms and real-time processing tasks.

Another key feature of the TMS320C6712D is its 32-bit fixed-point processing capabilities, which allows it to perform difficult mathematical computations efficiently. With an instruction set optimized for DSP applications, the processor includes specialized instructions for multiplying and accumulating operations, as well as support for advanced filtering and generation of audio signals.

The C6712D offers an extensive memory architecture, supporting up to 128 MB of external memory via a 32-bit data bus. It features on-chip SRAM, which provides fast access to data and program storage, enhancing the system's overall performance. Additionally, the device includes a powerful set of peripherals, such as dual asynchronous serial ports (UART), I2C interfaces, and DSP-specific interfaces that facilitate connectivity with other components and systems.

Power consumption is another vital aspect of the TMS320C6712D. It incorporates technologies allowing for low-power operation, which is essential for portable and battery-operated devices. The capability to operate in various power modes helps optimize performance while minimizing energy usage.

In conclusion, the Texas Instruments TMS320C6712D is a versatile and powerful DSP that excels in high-performance applications. Its VLIW architecture, fixed-point processing capabilities, extensive memory options, and low power consumption make it an ideal choice for engineers looking to implement complex signal processing tasks efficiently. Whether used in telecommunications, audio processing, or industrial applications, the C6712D remains a reliable and capable solution in the digital signal processing landscape.

Texas Instruments TMS320C6712D warranty Multichannel Buffered Serial Port Timing

Models: TMS320C6712D

MULTICHANNEL BUFFERED SERIAL PORT TIMING

timing requirements for McBSP†‡ (see Figure 41)

MIN

TMS320C6712D specifications