Texas Instruments TMS320C6712D warranty Input and Output Clocks, Timing requirements for CLKIN†‡§

SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005

		INPUT AND OUTPUT CLOCKS
timing requirements for CLKIN†‡§			(see Figure 21)
					−150
NO.				PLL MODE		BYPASS MODE		UNIT
				(PLLEN = 1)		(PLLEN = 0)
				MIN	MAX	MIN	MAX
1	tc(CLKIN)	Cycle time, CLKIN		6.7	83.3	6.7		ns
2	tw(CLKINH)	Pulse duration, CLKIN high		0.4C		0.4C		ns
3	tw(CLKINL)	Pulse duration, CLKIN low		0.4C		0.4C		ns
4	tt(CLKIN)	Transition time, CLKIN			5		5	ns

†The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.

‡C = CLKIN cycle time in ns. For example, when CLKIN frequency is 25 MHz, use C = 40 ns. § See the PLL and PLL Controller section of this data sheet.

1

4

2

CLKIN

3

4

Figure 21. CLKIN Timings

switching characteristics over recommended operating conditions for CLKOUT2ठ(see Figure 22)

NO.		PARAMETER	−150		UNIT
			MIN	MAX
1	tc(CKO2)	Cycle time, CLKOUT2	C2 − 0.8	C2 + 0.8	ns
2	tw(CKO2H)	Pulse duration, CLKOUT2 high	(C2/2) − 0.8	(C2/2) + 0.8	ns
3	tw(CKO2L)	Pulse duration, CLKOUT2 low	(C2/2) − 0.8	(C2/2) + 0.8	ns
4	tt(CKO2)	Transition time, CLKOUT2		2	ns

‡The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.

§C2 = CLKOUT2 period in ns. CLKOUT2 period is determined by the PLL controller output SYSCLK2 period, which must be set to CPU period divide-by-2.

1

4

2

CLKOUT2

3

4

Figure 22. CLKOUT2 Timings

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