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Texas Instruments TMS320C6712D warranty HOLD/HOLDA Timing, Hold Holda, Emif Bus† DSP Owns Bus

Models: TMS320C6712D

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SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005

HOLD/HOLDA TIMING

timing requirements for the HOLD/HOLDA cycles† (see Figure 37)

NO.
3	th(HOLDAL-HOLDL)Hold time, HOLD low after HOLDA low

†E = ECLKIN period in ns

−150

UNIT

MIN MAX

E

ns

switching characteristics over recommended operating conditions for the HOLD/HOLDA cycles†‡ (see Figure 37)

NO.			PARAMETER						−150		UNIT

									MIN	MAX


1	td(HOLDL-EMHZ)	Delay time,		low to EMIF Bus high impedance					2E	§	ns
			HOLD
2	td(EMHZ-HOLDAL)	Delay time, EMIF Bus high impedance to						low	0	2E	ns
						HOLDA
4	td(HOLDH-EMLZ)	Delay time,		high to EMIF Bus low impedance					2E	7E	ns
			HOLD
5	td(EMLZ-HOLDAH)	Delay time, EMIF Bus low impedance to					high		0	2E	ns
					HOLDA

†E = ECLKIN period in ns

‡ EMIF Bus consists of CE[3:0], BE[1:0], ED[15:0], EA[21:2], ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE.

§All pending EMIF transactions are allowed to complete before HOLDA is asserted. If no bus transactions are occurring, then the minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.

HOLD

HOLDA

EMIF Bus†

	DSP Owns Bus	External Requestor	DSP Owns Bus
	DSP Owns Bus	Owns Bus	DSP Owns Bus
		Owns Bus
		3
	2		5
	1		4
	C6712D		C6712D

†EMIF Bus consists of CE[3:0], BE[1:0], ED[15:0], EA[21:2], ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE.

Figure 37. HOLD/HOLDA Timing

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

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Image 81

Texas Instruments TMS320C6712D warranty HOLD/HOLDA Timing, Timing requirements for the HOLD/HOLDA cycles† see Figure, Hold

Contents

SPRS293A − October 2005 − Revised November Table of Contents Pages ADDITIONS/CHANGES/DELETIONS Revision HistoryMultichannel Buffered Serial Port Timing GDP and ZDP BGA package bottom view GDP and ZDP 272-PIN Ball Grid Array BGA PackageBottom View Description Characteristics of the C6712D Processor Device characteristicsHardware Features Internal Clock C6712DDevice compatibility Digital Signal Processor Functional block and CPU DSP core diagramCPU DSP core description DA1 ST1DA2 ST2Memory map summary Memory Map SummaryMemory Block Description Block Size Bytes HEX Address Range Emif Registers Peripheral register descriptionsL2 Cache Registers HEX Address Range Acronym Register NameDevice Registers Interrupt Selector RegistersEdma Parameter RAM† HEX Address Range Acronym Register Name CommentsQuick DMA Qdma and Pseudo Registers† Edma RegistersGpio Registers PLL Controller RegistersMcBSP0 and McBSP1 Registers HEX Address Range Acronym Register Name Comments TimerClkin CLKOUT3 CLKOUT2† CLKMODE0 Pllhv TMS TDO TDI TCK Trst Signal groups descriptionJtag BIG/LITTLE EndianCLKR1 TOUT1 TINP1CLKS1† GpioDevice configurations at device reset Device ConfigurationsBOOTMODE10 Configuration GDP/ZDP Functional Description PINEmifbe LendianDevcfg register description EksrcBIT # Name Description Terminal Functions PIN Signal Terminal FunctionsIPD Description Name GDP IPU‡ ZDP BOOTMODE1 C19 BOOTMODE0 C20 IPD BootmodeEMU1B9 EMU0D9 IPU LITTLE/BIG Endian FormatOnly one asserted during any external data access IPD Description Name GDP IPU‡ ZDP Resets and InterruptsEdge-driven Decoded from the two lowest bits of the internal addressEmif − Data # Emif − Address #TIMER0 TIMER1IPD Description Name GDP IPU‡ ZDP Emif − Data # Multichannel Buffered Serial Port 1 McBSP1Multichannel Buffered Serial Port 0 McBSP0 GENERAL-PURPOSE INPUT/OUTPUT Gpio ModuleReserved for Test RSV IPU IPD Description Name GDP IPU ZDPRSV IPD Additional Reserved for TestSPRS293A − October 2005 − Revised November See the power-supply decoupling portion of this data sheet Name GDP ZDP Supply Voltage PinsDvdd CvddGround Pins Description Name GDP ZDP Supply Voltage PinsVSS GNDVSS GND Signal Name PIN GDP ZDP TYPE†VSS Description GDP Name ZDP Ground PinsDevelopment support Software Development ToolsHardware Development Tools Device support Device and development-support tool nomenclatureFully qualified production device Prefix Temperature Range Default 0C to 90CDevice Family TechnologyDocumentation support Revision ID CPU CSR register descriptionPwrd PCC DCC Pgie GIECPU CSR Register Bit Field Description CPU IDPCC Cache configuration Ccfg register description Ccfg Register Bit Field DescriptionL2MODE Interrupt sources and interrupt selector DSP Interrupt Default Selector Module ControlDSP Interrupts Interrupt Selector EventEdma module and Edma selector Edma ChannelsEdma Selector ESEL3 Register 0x01A0 FF0C ESEL1 Register 0x01A0 FF04PLL and PLL controller Clkout Signals, Default Settings, and Control PLL Lock and Reset TimesEnabled or Disabled MIN TYP MAX UnitClock Signal PLL Clock Frequency Ranges†‡GDP 150and ZDP PLL Control/Status Register Pllcsr Pllcsr Register 0x01B7 C100PLL Multiplier Control Register Pllm Pllm Register 0x01B7 C110DxEN OSCDIV1 Register 0x01B7 C124 Oscillator Divider 1 Register OSCDIV1OD1EN General-purpose input/output Gpio GP7 GP6 GP5 GP4 GP2DIR Power-down mode logic PD3 PD2 PD1 Pwrd Field of the CSR RegisterCharacteristics of the Power-Down Modes Power-supply sequencingPower-supply design considerations System-level design considerationsSupply Schottky Diode Core Supply Power-supply decouplingGND Dvdd C6000Ieee 1149.1 Jtag compatibility statement Example Boards and Maximum Emif Speed Emif device speedBootmode Emif big endian mode correctnessReset Emif Data Lines Pins Where Data PresentRecommended operating conditions MIN NOM MAX UnitIOH IOZ Parameter Test Conditions MIN TYP MAX UnitParameter Measurement Information Signal transition levels42 Ω Vref = 1.5= 0.3 tcmax† VIL max VUS max Ground AC transient rise/fall time specificationsTiming parameters and board routing analysis Control Signals † Output from DSP Board-Level Timings Example see FigureOutput from DSP Input and Output Clocks Timing requirements for CLKIN†‡§See Figure Clkin CLKOUT3 Timing requirements for ECLKIN§ see FigureEclkin Eclkout MINTiming requirements for asynchronous memory cycles†‡ Asynchronous Memory TimingSee −Figure AreCE30 BE10 EA212 Setup = Strobe = Not Ready Hold =ED150 Read Data AOE/SDRAS/SSOE† ARE/SDCAS/SSADS† AWE/SDWE/SSWE† ArdyCEx BE30 EA212 ED310AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE † Ardy Unit MIN MAX SYNCHRONOUS-BURST Memory TimingBE1 BE2 BE3 BE4 CE30 BE10EA212 ED150 ARE/SDCAS/SSADS † AOE/SDRAS/SSOE † AWE/SDWE/SSWE†Synchronous Dram Timing Timing requirements for synchronous Dram cycles† see Figure150 Read Eclkout EA2113 Bank EA112 Column EA12 ED150AOE/SDRAS/SSOE † ARE/SDCAS/SSADS† AWE/SDWE/SSWE† EA2113 Write EclkoutEA12 ED150 AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE †CE30 BE10 EA2113 Bank Activate EA112 Row Address EA12 ED150 Actv EclkoutAOE/SDRAS/SSOE† ARE/SDCAS/SSADS† AWE/SDWE/SSWE† Dcab EclkoutCE30 BE10 EA2113 Deac EclkoutEA112 EA12 ED150 Refr EclkoutCE30 BE10 EA212 MRS value ED150 MRS EclkoutTiming requirements for the HOLD/HOLDA cycles† see Figure HOLD/HOLDA TimingHold Hold HoldaEclkout Busreq Busreq TimingReset Timing Timing requirements for reset†‡ see FigureCLKMODE0 = Emif Z Group † Emif Low Group † Boot and Device PhaseExternal Interrupt Timing Timing requirements for external interrupts† see FigureEXTINT, NMI Timing requirements for McBSP†‡ see Figure Multichannel Buffered Serial Port TimingParameter FSR int Clks ClkrBitn-1 ClkxClks Timing requirements for FSR when Gsync = 1 see FigureFSR external CLKR/X no need to resync CLKR/X needs resync Master Slave Unit MIN MAXParameter MASTER§ Slave Unit MIN MAX Clkx FSXBit Bitn-1 McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = Multichannel Buffered Serial Port Timing McBSP Timing as SPI Master or Slave Clkstp = 10b, Clkxp = McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = Timer Timing Timing requirements for timer inputs†TINPx TOUTx GENERAL-PURPOSE INPUT/OUTPUT Gpio Port Timing Timing requirements for Gpio inputs†‡GPIx GPOx Jtag TEST-PORT Timing Timing requirements for Jtag test port see FigureUnit MIN MAX TCK TDO TDI/TMS/TRST Thermal resistance characteristics S-PBGA package for GDP Package thermal resistance characteristicsThermal resistance characteristics S-PBGA package for ZDP Mechanical DataPackaging Information Orderable Device Status Package Pins Package Eco PlanMSL Peak Temp QtySeating Plane 4204396/A 04/02 GDP S-PBGA-N272Seating Plane 4204398/A 04/02 ZDP S-PBGA-N272Important Notice