Texas Instruments TMS320C6712D warranty HOLD/HOLDA Timing, Hold Holda, Emif Bus† DSP Owns Bus

SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005

HOLD/HOLDA TIMING

timing requirements for the HOLD/HOLDA cycles† (see Figure 37)

NO.
3	th(HOLDAL-HOLDL)Hold time, HOLD low after HOLDA low

†E = ECLKIN period in ns

−150

UNIT

MIN MAX

E ns

switching characteristics over recommended operating conditions for the HOLD/HOLDA cycles†‡ (see Figure 37)

NO.			PARAMETER						−150		UNIT
		MIN							MAX
1	td(HOLDL-EMHZ)	Delay time,		low to EMIF Bus high impedance					2E	§	ns
			HOLD
2	td(EMHZ-HOLDAL)	Delay time, EMIF Bus high impedance to						low	0	2E	ns
						HOLDA
4	td(HOLDH-EMLZ)	Delay time,		high to EMIF Bus low impedance					2E	7E	ns
			HOLD
5	td(EMLZ-HOLDAH)	Delay time, EMIF Bus low impedance to					high		0	2E	ns
					HOLDA

†E = ECLKIN period in ns

‡ EMIF Bus consists of CE[3:0], BE[1:0], ED[15:0], EA[21:2], ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE.

§All pending EMIF transactions are allowed to complete before HOLDA is asserted. If no bus transactions are occurring, then the minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.

HOLD

HOLDA

EMIF Bus†

DSP Owns Bus	External Requestor	DSP Owns Bus
	Owns Bus
	3
2		5
1		4
C6712D		C6712D

†EMIF Bus consists of CE[3:0], BE[1:0], ED[15:0], EA[21:2], ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE.

Figure 37. HOLD/HOLDA Timing

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