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Texas Instruments TMS320C6712D warranty AC transient rise/fall time specifications

Models: TMS320C6712D

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SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005

PARAMETER MEASUREMENT INFORMATION (CONTINUED)

AC transient rise/fall time specifications

Figure 18 and Figure 19 show the AC transient specifications for Rise and Fall Time. For device-specific information on these values, refer to the Recommended Operating Conditions section of this Data Sheet.

t = 0.3 tc (max)†

Minimum

Risetime

Waveform

Valid Region

Ground

VOS (max)

VIH (min)

Figure 18. AC Transient Specification Rise Time

†tc = the peripheral cycle time.

t = 0.3 tc(max)†

VIL (max)

VUS (max)

Ground

Figure 19. AC Transient Specification Fall Time

†tc = the peripheral cycle time.

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Texas Instruments TMS320C6712D warranty AC transient rise/fall time specifications, = 0.3 tcmax† VIL max VUS max Ground

Contents

SPRS293A − October 2005 − Revised November Table of Contents Revision History Pages ADDITIONS/CHANGES/DELETIONSMultichannel Buffered Serial Port Timing GDP and ZDP 272-PIN Ball Grid Array BGA Package GDP and ZDP BGA package bottom viewBottom View Description Device characteristics Characteristics of the C6712D ProcessorHardware Features Internal Clock C6712DDevice compatibility Functional block and CPU DSP core diagram Digital Signal ProcessorCPU DSP core description ST1 DA1DA2 ST2Memory Map Summary Memory map summaryMemory Block Description Block Size Bytes HEX Address Range Peripheral register descriptions Emif RegistersL2 Cache Registers HEX Address Range Acronym Register NameInterrupt Selector Registers Device RegistersEdma Parameter RAM† HEX Address Range Acronym Register Name CommentsEdma Registers Quick DMA Qdma and Pseudo Registers†PLL Controller Registers Gpio RegistersHEX Address Range Acronym Register Name Comments Timer McBSP0 and McBSP1 RegistersSignal groups description Clkin CLKOUT3 CLKOUT2† CLKMODE0 Pllhv TMS TDO TDI TCK TrstJtag BIG/LITTLE EndianTOUT1 TINP1 CLKR1CLKS1† GpioDevice Configurations Device configurations at device resetConfiguration GDP/ZDP Functional Description PIN BOOTMODE10Emifbe LendianEksrc Devcfg register descriptionBIT # Name Description Terminal Functions Terminal Functions PIN SignalIPD Description Name GDP IPU‡ ZDP Bootmode BOOTMODE1 C19 BOOTMODE0 C20 IPDEMU1B9 EMU0D9 IPU LITTLE/BIG Endian FormatIPD Description Name GDP IPU‡ ZDP Resets and Interrupts Only one asserted during any external data accessEdge-driven Decoded from the two lowest bits of the internal addressEmif − Address # Emif − Data #TIMER1 TIMER0IPD Description Name GDP IPU‡ ZDP Emif − Data # Multichannel Buffered Serial Port 1 McBSP1GENERAL-PURPOSE INPUT/OUTPUT Gpio Module Multichannel Buffered Serial Port 0 McBSP0Reserved for Test IPD Description Name GDP IPU ZDP RSV IPURSV IPD Additional Reserved for TestSPRS293A − October 2005 − Revised November Name GDP ZDP Supply Voltage Pins See the power-supply decoupling portion of this data sheetDvdd CvddDescription Name GDP ZDP Supply Voltage Pins Ground PinsVSS GNDSignal Name PIN GDP ZDP TYPE† VSS GNDDescription GDP Name ZDP Ground Pins VSSSoftware Development Tools Development supportHardware Development Tools Device and development-support tool nomenclature Device supportFully qualified production device Temperature Range Default 0C to 90C PrefixDevice Family TechnologyDocumentation support CPU CSR register description Revision IDPwrd PCC DCC Pgie GIECPU ID CPU CSR Register Bit Field DescriptionPCC Ccfg Register Bit Field Description Cache configuration Ccfg register descriptionL2MODE DSP Interrupt Default Selector Module Control Interrupt sources and interrupt selectorDSP Interrupts Interrupt Selector EventEdma Channels Edma module and Edma selectorEdma Selector ESEL1 Register 0x01A0 FF04 ESEL3 Register 0x01A0 FF0CPLL and PLL controller PLL Lock and Reset Times Clkout Signals, Default Settings, and ControlEnabled or Disabled MIN TYP MAX UnitPLL Clock Frequency Ranges†‡ Clock SignalGDP 150and ZDP Pllcsr Register 0x01B7 C100 PLL Control/Status Register PllcsrPllm Register 0x01B7 C110 PLL Multiplier Control Register PllmDxEN Oscillator Divider 1 Register OSCDIV1 OSCDIV1 Register 0x01B7 C124OD1EN GP7 GP6 GP5 GP4 GP2 General-purpose input/output GpioDIR Power-down mode logic Pwrd Field of the CSR Register PD3 PD2 PD1Power-supply sequencing Characteristics of the Power-Down ModesPower-supply design considerations System-level design considerationsPower-supply decoupling Supply Schottky Diode Core SupplyGND Dvdd C6000Ieee 1149.1 Jtag compatibility statement Emif device speed Example Boards and Maximum Emif SpeedEmif big endian mode correctness BootmodeReset Emif Data Lines Pins Where Data PresentMIN NOM MAX Unit Recommended operating conditionsIOH Parameter Test Conditions MIN TYP MAX Unit IOZSignal transition levels Parameter Measurement Information42 Ω Vref = 1.5AC transient rise/fall time specifications = 0.3 tcmax† VIL max VUS max GroundTiming parameters and board routing analysis Board-Level Timings Example see Figure Control Signals † Output from DSPOutput from DSP Timing requirements for CLKIN†‡§ Input and Output ClocksSee Figure Timing requirements for ECLKIN§ see Figure Clkin CLKOUT3MIN Eclkin EclkoutAsynchronous Memory Timing Timing requirements for asynchronous memory cycles†‡See −Figure AreSetup = Strobe = Not Ready Hold = CE30 BE10 EA212ED150 Read Data AOE/SDRAS/SSOE† ARE/SDCAS/SSADS† AWE/SDWE/SSWE† ArdyED310 CEx BE30 EA212AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE † Ardy SYNCHRONOUS-BURST Memory Timing Unit MIN MAXCE30 BE10 BE1 BE2 BE3 BE4EA212 ED150 ARE/SDCAS/SSADS † AOE/SDRAS/SSOE † AWE/SDWE/SSWE†Timing requirements for synchronous Dram cycles† see Figure Synchronous Dram Timing150 EA2113 Bank EA112 Column EA12 ED150 Read EclkoutAOE/SDRAS/SSOE † ARE/SDCAS/SSADS† AWE/SDWE/SSWE† Write Eclkout EA2113EA12 ED150 AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE †Actv Eclkout CE30 BE10 EA2113 Bank Activate EA112 Row Address EA12 ED150AOE/SDRAS/SSOE† ARE/SDCAS/SSADS† AWE/SDWE/SSWE† Dcab EclkoutDeac Eclkout CE30 BE10 EA2113EA112 EA12 ED150 Refr EclkoutMRS Eclkout CE30 BE10 EA212 MRS value ED150HOLD/HOLDA Timing Timing requirements for the HOLD/HOLDA cycles† see FigureHold Hold HoldaBusreq Timing Eclkout BusreqTiming requirements for reset†‡ see Figure Reset TimingCLKMODE0 = Phase Emif Z Group † Emif Low Group † Boot and DeviceTiming requirements for external interrupts† see Figure External Interrupt TimingEXTINT, NMI Multichannel Buffered Serial Port Timing Timing requirements for McBSP†‡ see FigureParameter Clks Clkr FSR intBitn-1 ClkxTiming requirements for FSR when Gsync = 1 see Figure ClksFSR external CLKR/X no need to resync CLKR/X needs resync Master Slave Unit MIN MAXClkx FSX Parameter MASTER§ Slave Unit MIN MAXBit Bitn-1 McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = Multichannel Buffered Serial Port Timing McBSP Timing as SPI Master or Slave Clkstp = 10b, Clkxp = McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = Timing requirements for timer inputs† Timer TimingTINPx TOUTx Timing requirements for Gpio inputs†‡ GENERAL-PURPOSE INPUT/OUTPUT Gpio Port TimingGPIx GPOx Timing requirements for Jtag test port see Figure Jtag TEST-PORT TimingUnit MIN MAX TCK TDO TDI/TMS/TRST Package thermal resistance characteristics Thermal resistance characteristics S-PBGA package for GDPThermal resistance characteristics S-PBGA package for ZDP Mechanical DataOrderable Device Status Package Pins Package Eco Plan Packaging InformationMSL Peak Temp QtyGDP S-PBGA-N272 Seating Plane 4204396/A 04/02ZDP S-PBGA-N272 Seating Plane 4204398/A 04/02Important Notice