Texas Instruments TMS320C6712D warranty Parameter Test Conditions MIN TYP MAX Unit, Ioz

SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005

electrical characteristics over recommended ranges of supply voltage and operating case temperature† (unless otherwise noted)

	PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
VOH	High-level output	All signals except CLKS1 and	DVDD = MIN, IOH = MAX	2.4			V
	voltage	DR1
	Low-level output	All signals except CLKS1 and				0.4	V
VOL		DR1	DVDD = MIN, IOL = MAX
	voltage
		CLKS1 and DR1				0.4	V
		All signals except CLKS1 and				±170	uA
II	Input current	DR1	VI = VSS to DVDD
		CLKS1 and DR1				±10	uA
	Off-state output	All signals except CLKS1 and				±170	uA
IOZ		DR1	VO = DVDD or 0 V
	current
		CLKS1 and DR1				±10	uA
I	Core supply current‡		CVDD = 1.26 V, CPU		430		mA
DD2V			clock = 150 MHz
IDD3V	I/O supply current‡		DVDD = 3.3 V,		75		mA
			EMIF speed = 100 MHz
Ci	Input capacitance	C6712D				7	pF
Co	Output capacitance	C6712D				7	pF

†For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table.

‡For more details on CPU, peripheral, and I/O activity, see the TMS320C62x/C67x Power Consumption Summary application report (literature

number SPRA486).

For the device, these currents were measured with average activity (50% high/50% low power) at 25°C case temperature and 100-MHz EMIF. This model represents a device performing high-DSP-activity operations 50% of the time, and the remainder performing low-DSP-activity operations. The high/low-DSP-activity models are defined as follows:

High-DSP-Activity Model:

CPU: 8 instructions/cycle with 2 LDDW instructions [L1 Data Memory: 128 bits/cycle via LDDW instructions;

L1 Program Memory: 256 bits/cycle; L2/EMIF EDMA: 50% writes, 50% reads to/from SDRAM (50% bit-switching)] McBSP: 2 channels at E1 rate

Timers: 2 timers at maximum rate Low-DSP-Activity Model:

CPU: 2 instructions/cycle with 1 LDH instruction [L1 Data Memory: 16 bits/cycle; L1 Program Memory: 256 bits per 4 cycles; L2/EMIF EDMA: None]

McBSP: 2 channels at E1 rate

Timers: 2 timers at maximum rate

The actual current draw is highly application-dependent. For more details on core and I/O activity, refer to the TMS320C6711D/12D/13B Power Consumption Summary application report (literature number SPRA889A).

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