SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005

 

 

 

 

 

Terminal Functions (Continued)

 

PIN

 

 

 

 

 

SIGNAL

NO.

TYPE

 

IPD/

 

DESCRIPTION

 

 

 

NAME

GDP/

 

IPU

 

 

 

 

 

 

ZDP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EMIF − DATA (CONTINUED) #

ED9

P18

I/O/Z

 

IPU

 

External data

 

 

 

 

ED8

N20

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ED7

N19

 

 

 

 

 

 

 

 

 

 

 

 

ED6

N18

 

 

 

 

 

 

 

 

 

 

 

 

ED5

M20

 

 

 

 

 

 

 

 

 

 

 

 

ED4

M19

I/O/Z

 

IPU

 

External data

 

 

 

 

ED3

L19

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ED2

L18

 

 

 

 

 

 

 

 

 

 

 

 

ED1

K19

 

 

 

 

 

 

 

 

 

 

 

 

ED0

K18

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TIMER1

 

 

 

 

 

 

 

TOUT1

F1

O

 

IPD

 

Timer 1 or general-purpose output

 

 

 

 

 

 

 

TINP1

F2

I

 

IPD

 

Timer 1 or general-purpose input

 

 

 

 

 

 

 

 

 

 

 

 

 

TIMER0

 

 

 

 

 

 

 

TOUT0

G1

O

 

IPD

 

Timer 0 or general-purpose output

 

 

 

 

 

 

 

TINP0

G2

I

 

IPD

 

Timer 0 or general-purpose input

 

 

 

 

 

 

 

 

 

MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1)

 

 

 

 

 

 

 

 

 

 

 

 

 

External clock source (as opposed to internal)

 

 

 

 

 

 

On this device, this pin does not have an internal pulldown (IPD). For proper device opera-

CLKS1

E1

I

 

IPD

 

tion, the CLKS1 pin should either be driven externally at all times or be pulled up with a

 

 

10-kresistor to a valid logic level. Because it is common for some ICs to 3-state their out-

 

 

 

 

 

 

 

 

 

 

 

 

puts at times, a 10-kpullup resistor may be desirable even when an external device is

 

 

 

 

 

 

driving the pin.

 

 

 

 

 

 

 

CLKR1

M1

I/O/Z

 

IPD

 

Receive clock

 

 

 

 

 

 

 

CLKX1

L3

I/O/Z

 

IPD

 

Transmit clock

 

 

 

 

 

 

 

 

 

 

 

 

 

Receive data

 

 

 

 

 

 

On this device, this pin does not have an internal pullup (IPU). For proper device operation,

DR1

M2

I

 

IPU

 

the DR1 pin should either be driven externally at all times or be pulled up with a 10-kresis-

 

 

 

 

 

 

tor to a valid logic level. Because it is common for some ICs to 3-state their outputs at times,

 

 

 

 

 

 

a 10-kpullup resistor may be desirable even when an external device is driving the pin.

 

 

 

 

 

 

 

DX1

L2

O/Z

 

IPU

 

Transmit data

 

 

 

 

 

 

 

FSR1

M3

I/O/Z

 

IPD

 

Receive frame sync

 

 

 

 

 

 

 

FSX1

L1

I/O/Z

 

IPD

 

Transmit frame sync

I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal (PLL Filter)

IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors no greater than 4.4 kand 2.0 k, respectively.]

#To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.

28

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Page 28
Image 28
Texas Instruments TMS320C6712D warranty IPD Description Name GDP IPU‡ ZDP Emif − Data #, TIMER1, TIMER0

TMS320C6712D specifications

The Texas Instruments TMS320C6712D is a high-performance, fixed-point digital signal processor (DSP) that belongs to the TMS320C6000 family, well known for its advanced processing capabilities tailored for demanding signal processing applications. Launched in the early 2000s, the C6712D combines high computational power with a rich set of features, making it suitable for a variety of applications such as telecommunications, audio processing, and industrial control systems.

One of the standout characteristics of the TMS320C6712D is its architecture, which is based on a highly efficient VLIW (Very Long Instruction Word) design. This architecture allows the processor to execute multiple instructions in a single clock cycle, significantly increasing performance. The device operates at clock speeds of up to 150 MHz, providing substantial computational throughput that can handle complex algorithms and real-time processing tasks.

Another key feature of the TMS320C6712D is its 32-bit fixed-point processing capabilities, which allows it to perform difficult mathematical computations efficiently. With an instruction set optimized for DSP applications, the processor includes specialized instructions for multiplying and accumulating operations, as well as support for advanced filtering and generation of audio signals.

The C6712D offers an extensive memory architecture, supporting up to 128 MB of external memory via a 32-bit data bus. It features on-chip SRAM, which provides fast access to data and program storage, enhancing the system's overall performance. Additionally, the device includes a powerful set of peripherals, such as dual asynchronous serial ports (UART), I2C interfaces, and DSP-specific interfaces that facilitate connectivity with other components and systems.

Power consumption is another vital aspect of the TMS320C6712D. It incorporates technologies allowing for low-power operation, which is essential for portable and battery-operated devices. The capability to operate in various power modes helps optimize performance while minimizing energy usage.

In conclusion, the Texas Instruments TMS320C6712D is a versatile and powerful DSP that excels in high-performance applications. Its VLIW architecture, fixed-point processing capabilities, extensive memory options, and low power consumption make it an ideal choice for engineers looking to implement complex signal processing tasks efficiently. Whether used in telecommunications, audio processing, or industrial applications, the C6712D remains a reliable and capable solution in the digital signal processing landscape.