Introduction

Status and configuration space

The status and configuration space contains status and configuration registers for the core module. These provide the following information and control:

•type of processor and whether it has a cache, MMU, or protection unit

•the position of the core module in a multi-module stack

•SDRAM size, address configuration, and CAS latency setup

•core module oscillator setup

•interrupt control for the processor debug communications channel.

The status and control registers can only be accessed by the local processor. For more information about the status and control registers see Chapter 4 Programmer’s Reference.

1.2.3Volatile memory

The volatile memory system includes an SSRAM device, and a plug-in SDRAM memory module (referred to as local SDRAM when it is on the same core module as the processor). These areas of memory are closely coupled to the processor core to ensure high performance. The core module uses separate memory and system buses to avoid memory access performance being degraded by bus loading.

The SDRAM controller is implemented within the core module controller FPGA and a separate SSRAM controller is implemented with a Programmable Logic Device (PLD).

The SDRAM can be accessed by the local processor, by processors on other core modules, and by other system bus masters.

The SSRAM can only be accessed by the local processor.

1.2.4Clock generator

The core module uses two on-board clocks:

•CPU clock up to 160MHz

•memory bus clock up to 66MHz.

These clocks are supplied by two clock generator chips. Their frequencies are selected via the oscillator control register (CM_OSC) within the FPGA. A reference clock is supplied to the two clock generators and to the FPGA (see Clock generators on page 3-17). The memory bus and system bus are asynchronous. This allows each bus to be run at the speed of its slowest device without compromising the performance of other buses in the system.

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