Hardware Description

3.1ARM940T microprocessor core

The ARM940T cached processor macrocell is a member of the ARM9 Thumb family of high-performance 32-bit system-on-a-chip processors. It provides the following:

•ARM9TDMI RISC integer CPU

•4KB instruction and data caches

•write buffer

•protection unit

•AMBA ASB bus interface.

The ARM940T processor employs a Harvard cache architecture, and so has separate 4KB instruction and 4KB data caches. Each cache has a 4-word line length.

The protection unit allows eight regions of memory to be defined, each with individual cache and write buffer configurations and access permissions.

The cache system is software-configurable to provide highest average performance or to meet the needs of real-time systems. Software configurable options include:

•random or round-robin cache line replacement algorithm

•write-through or writeback cache operation

•cache locking with granularity 1/64 th of cache size.

The caches and write buffers improve CPU performance and minimize accesses to off-chip memory, thus reducing overall system power consumption. The ARM940T includes support for coprocessors, allowing a floating point unit or other application-specific hardware acceleration to be added.

The ARM9TDMI core executes both the 32-bit ARM and 16-bit Thumb instruction sets, allowing you to trade between high performance and high code density. It is binary-compatible with ARM7TDMI, ARM10TDMI, and StrongARM processors, and is supported by a wide range of tools, operating systems, and application software.

The ARM940T also features a TrackingICE mode which allows an approach similar to a conventional ICE mode of operation.

For more information about the ARM940T, refer to the ARM940T Technical Reference Manual.

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