ARM CM940T 75

Programmer’s Reference

Example 4-1

CM_BASE	EQU	0x10000000		; base address of Core Module registers
SPD_BASE	EQU	0x10000100		; base address of SPD information
lightled
		; turn on header LED and remap memory
	LDR	r0, =CM_BASE		; load register base address
	MOV	r1,#5		; set remap and led bits
	STR	r1,[r0,#0xc]		; write the register
		; setup SDRAM
readspdbit
		; check SPD bit		is set
	LDR	r1,[r0,#0x20]		; read the status register
	AND	r1,r1,#0x20		; mask SPD bit (5)
	CMP	r1,#0x20		; test if set
	BNE	readspdbit		; branch until the SPD memory has been read
setupsdram
		; work out the	SDRAM size
	LDR	r0, =SPD_BASE	;	point at SPD memory
	LDRB	r1,[r0,#3]	;	number of row address lines
	LDRB	r2,[r0,#4]	;	number of column address lines
	LDRB	r3,[r0,#5]	;	number of banks
	LDRB	r4,[r0,#31]	;	module bank density
	MUL	r5,r4,r3	;	calculate size of SDRAM (MB divided by 4)
	MOV	r5,r5,ASL#2	;	size in MB
	CMP	r5,#0x10	;	is it 16MB?
	BNE	not16	;	if no, move on
	MOV	r6,#0x2	;	store size and CAS latency of 2
	B	writesize
not16
	CMP	r5,#0x20	;	is it 32MB?
	BNE	not32	;	if no, move on
	MOV	r6,#0x6	;	store size and CAS latency of 2
	B	writesize
not32
	CMP	r5,#0x40	;	is it 64MB?
	BNE	not64	;	if no, move on
	MOV	r6,#0xa	;	store size and CAS latency of 2
	B	writesize

ARM DUI 0125A

4-17