Hardware Description

a 64 x 32-bit area of memory (CM_SPD) within the SDRAM controller. The SPD flag is set in the SDRAM control register (CM_SDRAM) when the SPD data is available. This copy can be randomly accessed at 0x10000100 to 0x100001FC (see CM_SPD (0x10000100 to 0x100001FC) on page 4-16).

Write accesses to the SPD EEPROM are not supported.

ARM DUI 0125A

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