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ARM CM940T manual 58

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Hardware Description

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© Copyright ARM Limited 1999. All rights reserved.

ARM DUI 0125A

Contents

Page ARM Integrator/CM940T User Guide Electromagnetic conformity Page ARM Integrator/CM940T User Guide Programmer’s Reference Appendix A Signal Descriptions Appendix B Specifications Page About this document Typographical conventions bold Further reading Feedback Page Introduction 1.1About the ARM Integrator/CM940T core module Page 1.2ARM Integrator/CM940T overview 1.2.2Core module FPGA SDRAM controller Reset controller System bus bridge Status and configuration space 1.2.3Volatile memory 1.2.4Clock generator 1.2.5Multi-ICEconnector nTRST Note 1.3Links and indicators 1.3.2LED indicators 1.4Test points 1.5Precautions Page Getting Started 2.1Setting up a standalone ARM Integrator/CM940T 2.1.3Supplying power 2.1.4Connecting Multi-ICE ICE 2.2Attaching the ARM Integrator/CM940T to a motherboard 2.2.1Core module ID 2.2.2Powering the assembled Integrator development system Hardware Description 3.1ARM940T microprocessor core 3.2SSRAM controller 3.3Core module FPGA Page 3.4SDRAM controller Page 3.5Reset controller 3.5.1Reset signals 3.5.2Software resets SWRST 3.6System bus bridge Processor reads 3.6.2Motherboard accesses to SDRAM System bus writes System bus reads 3.6.3Multiprocessor 3.6.4System bus signal routing HDRA HDRB 3.6.5Bus operating modes 3.7Clock generators 3.7.1Processor core clock (CORECLK) 3.7.2Processor bus clocks (LCLK and nLCLK) 3.7.3FPGA reference clock (REFCLK) 3.8Multi-ICEsupport 3.8.1JTAG scan path 3.8.2Debugging modes Normal debug mode Configuration mode 3.8.3JTAG signals Page Page 3.8.4Debug communications interrupts Page Programmer’s Reference 4.1Memory organization Motherboard detect 4.1.3SDRAM accesses Local SDRAM System bus accesses to SDRAM System bus address Local address 4.2Exception vector mapping 4.3Core module registers 4.3.1CM_ID (0x10000000) 4.3.2CM_PROC (0x10000004) 4.3.3CM_OSC (0x10000008) Page 4.3.4CM_CTRL (0x1000000C) 4.3.5CM_STAT (0x10000010) 4.3.6CM_LOCK (0x10000014) 4.3.7CM_SDRAM (0x10000020) Page 4.3.8CM_SPD (0x10000100 to 0x100001FC) Page Page 4.4Interrupt registers 4.4.1CM_IRQ_STAT (0x10000040)/CM_FIQ_STAT (0x10000060) 4.4.2CM_IRQ_RSTAT (0x10000044)/CM_FIQ_RSTAT (0x10000064) 4.4.3CM_IRQ_ENSET (0x10000048)/CM_FIQ_ENSET (0x10000068) 4.4.4CM_IRQ_ENCLR(0x1000004C)/CM_FIQ_ENCLR (0x1000006C) 4.4.5Interrupt register bit assignment 4.4.6CM_SOFT_INTSET (0x10000050)/CM_SOFT_INTCLT (0x10000054) Signal Descriptions A.1 HDRA Page A.2 HDRB A.2.2 HDRB plug pinout A.2.3 Through-boardsignal connections A.2.4 HDRB signal descriptions SYSCLK[3:0] nPPRES[3:0] nIRQ[3:0] nFIQ[3:0] MASTER[2:0] Specifications B.1 Electrical specification B.2 Timing specification B.3 Mechanical details