ARM CM940T B.2 Timing specification

Specifications

B.2 Timing specification

Table B-2provides the operating timing characteristics for the system bus interface signals.

Table B-2 Core module timing (preliminary)

Symbol	Description	Min	Max	Units
FMAX	Operating frequency	-	25	MHz
TCH	Clock HIGH	19	-	ns
TCL	Clock LOW	19	-	ns
TCO	Clock to output – signals generated and	-	16.0	ns
	sampled on same clock edge
	Clock to output – signals generated and	-	8.0	ns
	sampled on different clock edge
TIC	Input to clock – signals generated and	-	8.0	ns
	sampled on same clock edge
	Input to clock – signals generated and	-	4.0	ns
	sampled on different clock edge
TBPD	Motherboard propagation delay (for	-	1.0	ns
	guidance only)
TSKEW	Motherboard clock skew for guidance	-	1.0	ns
	only)

ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. B-3