Programmer’s Reference
4.3Core module registers
The core module status and control registers allow the processor to determine its environment and to control some core module operations. The registers, listed in Table
Table
Register Name | Address | Access | Description |
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CM_ID | 0x10000000 | Read | Core module identification register |
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CM_PROC | 0x10000004 | Read | Core module processor register |
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CM_OSC | 0x10000008 | Read/write | Core module oscillator values |
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CM_CTRL | 0x1000000C | Read/write | Core module control |
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CM_STAT | 0x10000010 | Read | Core module status |
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CM_LOCK | 0x10000014 | Read/write | Core module lock |
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CM_SDRAM | 0x10000020 | Read/write | SDRAM status and control |
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CM_IRQ_STAT | 0x10000040 | Read | Core module IRQ status register |
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CM_IRQ_RSTAT | 0x10000044 | Read | Core module IRQ raw status register |
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CM_IRQ_ENSET | 0x10000048 | Read/write | Core module IRQ enable set register |
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CM_IRQ_ENCLR | 0x1000004C | Write | Core module IRQ enable clear register |
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CM_SOFT_INTSET | 0x10000050 | Read/write | Core module software interrupt set |
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CM_SOFT_INTCLR 0x10000054 | Write | Core module software interrupt clear | |
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CM_FIQ_STAT | 0x10000060 | Read | Core module FIQ status register |
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CM_FIQ_RSTAT | 0x10000064 | Read | Core module FIQ raw status register |
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CM_FIQ_ENSET | 0x10000068 | Read/write | Core module FIQ enable set register |
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CM_FIQ_ENCLR | 0x1000006C | Write | Core module FIR enable clear register |
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CM_SPD | 0x10000100 to 0x100001FC | Read | SDRAM SPD memory |
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Note
All registers are
ARM DUI 0125A | © Copyright ARM Limited 1999. All rights reserved. |