Hardware Description

The configuration mode allows FPGA and PLD code to be updated as follows:

•The FPGAs are volatile, but load their configuration from flash memory. Flash memory, which itself does not have a JTAG port, can be programmed by loading designs into the FPGAs and PLDs which handle the transfer of data to the flash using JTAG.

•The PLDs are non-volatile devices which can be programmed directly by JTAG.

3.8.3JTAG signals

Figure 3-12shows the pinout of the Multi-ICE connector and Table 3-4 on page 3-25provides a description of the JTAG signals.

 

 

 

 

 

 

 

 

3V3

 

 

1

2

 

 

3V3

 

 

 

 

 

 

nTRST

 

 

 

 

 

 

GND

TDI

 

 

 

 

 

 

GND

TMS

 

 

 

 

 

 

GND

TCK

 

 

 

 

 

 

GND

RTCK

 

 

 

 

 

 

GND

TDO

 

 

 

 

 

 

GND

nSRST

 

 

 

 

 

 

GND

DBGRQ

 

 

 

 

 

 

GND

DBGACK

 

 

19

20

 

 

GND

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 3-12 Multi-ICE connector pinout

Note

In the description in Table 3-4 on page 3-25,the term JTAG equipment refers to any hardware that can drive the JTAG signals to devices in the scan chain. In most cases this will be Multi-ICE, although hardware from third-party suppliers can also be used to debug ARM processors.

3-24

© Copyright ARM Limited 1999. All rights reserved.

ARM DUI 0125A