ARM CM940T TDO, TDI, TMS, RTCK, nSRST, nTRST, nCFGEN, ID[3:0], nRTCKEN, nSYSRST, Reserved, FPGADONE, nIRQ[3:0], nFIQ[3:0], AGNT[3:0], AREQ[3:0], SYSCLK[3:0]

Signal Descriptions

A.2.4 HDRB signal descriptions

Table A-3describes the signals on the pins labeled E[31:0], F[31:0], and G[15:0].

		Table A-3 HDRB signal description

Pin label	Name	Description

E[31:28]	SYSCLK[3:0]	System clock (ASB clock) to each core
		module/expansion card

E[27:24]	nPPRES[3:0]	Processor present

E[23:20]	nIRQ[3:0]	Interrupt request to processors 3, 2, 1, and 0
		respectively

E[19:16]	nFIQ[3:0]	Fast interrupt requests to processors 3, 2, 1, and
		0 respectively

E[15:12]	ID[3:0]	Core module stack position indicator

E[11:8]	Reserved	-

E[7:4]	AGNT[3:0]	System bus grant

E[3:0]	AREQ[3:0]	System bus request

F[31:0]	-	Not connecetd

G16	nRTCKEN	RTCK AND gate enable

G[15:14]	CFGSEL[1:0]	FPGA configuration select

G13	nCFGEN	Sets motherboard into configuration mode

G12	nSRST	Multi-ICE reset (open collector)

G11	FPGADONE	Indicates when FPGA configurarion is
		complete (open collector)

G10	RTCK	Returned JTAG test clock

G9	nSYSRST	Buffered system reset

G8	nTRST	JTAG reset

G7	TDO	JTAG test data out

G6	TDI	JTAG test data in

G5	TMS	JTAG test mode select

ARM DUI 0125A

A-7