Hardware Description

At power-up the FPGA loads its configuration data from a flash memory device. Parallel data from the flash is serialized by the Programmable Logic Device (PLD) into the configuration inputs of the FPGA. Figure 3-2shows the FPGA configuration mechanism.

 

 

 

 

 

A[18:0]

 

 

 

 

 

 

 

 

 

DIN

 

 

D[7:0]

FPGA

 

 

CCLK

PLD

OE

FPGA

configuration

DONE

 

 

WE

ROM

 

 

 

 

 

 

 

 

(flash)

 

 

 

 

 

CS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Multi-ICE

Figure 3-2 FPGA configuration

Multi-ICE can be used to reprogram the PLD, FPGA, and flash when the core module is placed in configuration mode. See Multi-ICE support on page 3-21.

ARM DUI 0125A

© Copyright ARM Limited 1999. All rights reserved.

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