ARM CM940T SWRST, nSRST, 3.5.2Software resets

Hardware Description

3.5.2Software resets

The core module FPGA provides a software reset which can be triggered by writing to the reset bit in the CM_CTRL register. This generates the internal reset signal SWRST which generates nSRST and resets the whole system (see CM_CTRL (0x1000000C) on page 4-11).

3-10 © Copyright ARM Limited 1999. All rights reserved. ARM DUI 0125A