Ultra37000 CPLD Family
Document #: 38-03007 Rev. *E Page 11 of 64
Logic Block Diagrams (continued)

CY37256/CY37256V

LOGIC
BLOCK
G
LOGIC
BLOCK
H
LOGIC
BLOCK
I
LOGIC
BLOCK
J
LOGIC
BLOCK
L
LOGIC
BLOCK
P
LOGIC
BLOCK
M
LOGIC
BLOCK
N
LOGIC
BLOCK
O
LOGIC
BLOCK
A
LOGIC
BLOCK
B
LOGIC
BLOCK
C
LOGIC
BLOCK
D
LOGIC
BLOCK
E
LOGIC
BLOCK
K
LOGIC
BLOCK
F
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
PIM
Input
Clock/
Input
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
I/O0−I/O11
I/O12−I/O23
I/O24−I/O35
I/O36−I/O47
I/O48−I/O59
I/O60−I/O71
I/O72−I/O83
I/O84−I/O95
I/O180−I/O191
I/O168−I/O179
I/O156−I/O167
I/O144−I/O155
I/O132−I/O143
I/O120−I/O131
I/O108−I/O119
I/O96−I/O107
4
4
4
96
96
TDI
TCK
TMS TDO
JTAG Tap
Controller
1
[+] Feedback