Cypress 37000 CPLD manual Logic Block Diagrams, CY37256/CY37256V

Ultra37000 CPLD Family

Logic Block Diagrams (continued)

Clock/

CY37256/CY37256V

Input

Input

1

4

4

36

36

4

12 I/Os

LOGIC

LOGIC

12 I/Os

I/O

−I/O

BLOCK

16

16

BLOCK

I/O180−I/O191

0

11

A

36

36

P

12 I/Os

LOGIC

LOGIC

12 I/Os

I/O12−I/O23

BLOCK

16

16

BLOCK

I/O168−I/O179

B

36

36

O

12 I/Os

LOGIC

LOGIC

12 I/Os

I/O24−I/O35

BLOCK

16

16

BLOCK

I/O156−I/O167

C

36

36

N

12 I/Os

LOGIC

LOGIC

12 I/Os

I/O36−I/O47

BLOCK

16

16

BLOCK

I/O144−I/O155

D

36

PIM

36

M

12 I/Os

LOGIC

LOGIC

12 I/Os

I/O48−I/O59

BLOCK

16

16

BLOCK

I/O132−I/O143

E

36

36

L

12 I/Os

LOGIC

LOGIC

12 I/Os

I/O60−I/O71

BLOCK

16

16

BLOCK

I/O120−I/O131

F

36

36

K

12 I/Os

LOGIC

LOGIC

12 I/Os

I/O72−I/O83

BLOCK

16

16

BLOCK

I/O

−I/O

119

G

J

108

36

36

12 I/Os

LOGIC

LOGIC

12 I/Os

I/O

84

−I/O

95

BLOCK

16

16

BLOCK

I/O96−I/O107

H

I

TDI

JTAG Tap

TDO

96

96

TCK

Controller

TMS

Document #: 38-03007 Rev. *E Page 11 of 64

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