Cypress 37000 CPLD - page 18

Ultra37000 CPLD Family
Document #: 38-03007 Rev. *E Page 18 of 64
Product Term Clocking Parameters
tCOPT[13, 14, 15] Product Term Clock or Latch Enable (PTCLK) to Output ns
tSPT Set-Up Time from Input to Product Term Clock or Latch Enable (PTCLK) ns
tHPT Register or Latch Data Hold Time ns
tISPT[13] Set-Up Time for Buried Register used as an Input Register from Input to Product Term Clock or
Latch Enable (PTCLK) ns
tIHPT Buried Register Used as an Input Register or Latch Data Hold Time ns
tCO2PT[13, 14, 15] Product Term Clock or Latch Enable (PTCLK) to Output Delay (Through Logic Array) ns
Pipelined Mode Parameters
tICS[13] Input Register Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) to Output Register Synchronous
Clock (CLK0, CLK1, CLK2, or CLK3)ns
Operating Frequency Parameters
fMAX1 Maximum Frequency with Internal Feedback (Lesser of 1/tSCS, 1/(tS + tH), or 1/tCO)[5] MHz
fMAX2 Maximum Frequency Data Path in Output Registered/Latched Mode (Lesser of 1/(tWL + tWH),
1/(tS+t
H), or 1/tCO)[5] MHz
fMAX3 Maximum Frequency with External Feedback (Lesser of 1/(tCO + tS) or 1/(tWL + tWH)[5] MHz
fMAX4 Maximum Frequency in Pipelined Mode (Lesser of 1/(tCO + tIS), 1/tICS, 1/(tWL + tWH), 1/(tIS + tIH),
or 1/tSCS)[5] MHz
Reset/Preset Parameters
tRW Asynchronous Reset Width[5] ns
tRR[13] Asynchronous Reset Recovery Time[5] ns
tRO[13, 14, 15] Asynchronous Reset to Output ns
tPW Asynchronous Preset Width[5] ns
tPR[13] Asynchronous Preset Recovery Time[5] ns
tPO[13, 14, 15] Asynchronous Preset to Output ns
User Option Parameters
tLP Low Power Adder ns
tSLEW Slow Output Slew Rate Adder ns
t3.3IO 3.3V I/O Mode Timing Adder[5] ns
JTAG Timing Parameters
tS JTAG Set-up Time from TDI and TMS to TCK[5] ns
tH JTAG Hold Time on TDI and TMS[5] ns
tCO JTAG Falling Edge of TCK to TDO[5] ns
fJTAG Maximum JTAG Tap Controller Frequency[5] ns
Switching Characteristics Over the Operating Range (continued)[12]
Parameter Description Unit
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