Ultra37000 CPLD Family
Document #: 38-03007 Rev. *E Page 17 of 64
Parameter[11] VXOutput Waveform—Measurement Level
tER(–) 1.5V
tER(+) 2.6V
tEA(+) 1.5V
tEA(–) Vthe
(d) Test Waveforms
VOH VX
0.5V
VOL
VX
0.5V
VX
VOH
0.5V
VXVOL
0.5V
Switching Characteristics Over the Operating Range [12]
Parameter Description Unit
Combinatorial Mode Parameters
tPD[13, 14, 15] Input to Combinatorial Output ns
tPDL[13, 14, 15] Input to Output Through Transparent Input or Output Latch ns
tPDLL[13, 14, 15] Input to Output Through Transparent Input and Output Latches ns
tEA[13, 14, 15] Input to Output Enable ns
tER[11, 13] Input to Output Disable ns
Input Register Parameters
tWL Clock or Latch Enable Input LOW Time[8] ns
tWH Clock or Latch Enable Input HIGH Time[8] ns
tIS Input Register or Latch Set-up Time ns
tIH Input Register or Latch Hold Time ns
tICO[13, 14, 15] Input Register Clock or Latch Enable to Combinatorial Output ns
tICOL[13, 14, 15] Input Register Clock or Latch Enable to Output Through Transparent Output Latch ns
Synchronous Clocking Parameters
tCO[14, 15] Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable to Output ns
tS[13] Set-Up Time from Input to Sync. Clk (CLK0, CLK1, CLK2, or CLK3) or Latch Enable ns
tHRegister or Latch Data Hold Time ns
tCO2[13, 14, 15] Output Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable to Combinatorial Output
Delay (Through Logic Array)
ns
tSCS[13] Output Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable to Output Synchronous
Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable (Through Logic Array)
ns
tSL[13] Set-Up Time from Input Through Transparent Latch to Output Register Synchronous Clock (CLK0
CLK1, CLK2, or CLK3) or Latch Enable
ns
tHL Hold Time for Input Through Transparent Latch from Output Register Synchronous Clock (CLK0,
CLK1, CLK2, or CLK3) or Latch Enable
ns
Notes:
11.t ER measured with 5-pF AC Test Load and tEA measured with 35-pF AC Test Load.
12.All AC parameters are measured with two outputs switching and 35-pF AC Test Load.
13.Logic Blocks operating in Low-Power Mode, add tLP to this spec.
14.Outputs using Slow Output Slew Rate, add tSLEW to this spec.
15.When VCCO = 3.3V, add t3.3IO to this spec.
[+] Feedback