Cypress 37000 CPLD CY37192V, CY37256V

Ultra37000 CPLD Family
Document #: 38-03007 Rev. *E Page 29 of 64
CY37192V
CY37256V
Typical 3.3V Power Consumption (continued)
0
20
40
60
80
100
120
0 20 40 60 80 100 120
Frequency (MHz)
Icc (mA)
Low Power
High Speed
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 3.3V, TA = Room Temperature
0
20
40
60
80
100
120
140
0 20 40 60 80 100 120
Frequency (MHz)
Icc (mA)
Low Power
High Speed
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 3.3V, TA = Room Temperature
[+] Feedback