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Cypress 37000 CPLD Latched Input and Output, Asynchronous Reset, Output Enable/Disable, Asynchronous Preset

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Ultra37000 CPLD Family

Document #: 38-03007 Rev. *E Page 23 of 64

Latched Input and OutputAsynchronous ResetAsynchronous PresetOutput Enable/Disable

Switching Waveforms (continued)

tICS

LATCHED INPUT

OUTPUT LATCH

ENABLE

LATCHED

OUTPUT

tPDLL

LATCHENABLE

tWL

tWH

tICOL

INPUT LATCH

ENABLE

tSL tHL

INPUT

tRO

REGISTERED

OUTPUT

CLOCK

tRR

tRW

INPUT

tPO

REGISTERED

OUTPUT

CLOCK

tPR

tPW

INPUT

tER

OUTPUTS

tEA

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Contents

Main 5V, 3.3V, ISR High-Performance CPLDs Features General Description Selection Guide Ultra37000 CPLD Family Architecture Overview of Ultra37000 Family Page Page Page Ultra37000 CPLD Family JTAG and PCI Standards Development Software Support Page Logic Block Diagrams CY37032/CY37032V PIM PIM CY37064/CY37064V PIM C E D B PIM CY37384/CY37384V PIM CY37512/CY37512V PIM 5.0V Device Characteristics Maximum Ratings Operating Range 5.0V Device Electrical Characteristics 3.3V Device Characteristics Maximum Ratings Inductance Capacitance Endurance Characteristics Operating Range Inductance Capacitance Endurance Characteristics AC Characteristics V OH V V V X V Page Page Switching Characteristics Switching Waveforms Registered Output with Product Term Clocking Input Going Through the Array Registered Output with Product Term Clocking Input Coming From Adjacent Buried Register Latched Output Registered Input Clock to Clock Latched Input Latched Input and Output Asynchronous Reset Output Enable/Disable Asynchronous Preset Power Consumption Typical 5.0V Power Consumption CY37032 Low Power Icc (mA) Icc (mA) CY37128 CY37192 CY37256 Low Power Low Power Icc (mA) Icc (mA) CY37512 Typical 3.3V Power Consumption CY37032V CY37064V Low Power Low Power Icc (mA) Icc (mA) CY37192V Low Power Low Power Icc (mA) Icc (mA) Document #: 38-03007 Rev. *E Page 30 of 64 CY37384V Low Power Icc (mA) Low Power Pin Configurations 44-pin TQFP (A44) 44-pin PLCC (J67) / CLCC (Y67) Note: 20.For 3.3V versions (Ultra37000V), VCCO = VCC. 48-ball Fine-Pitch BGA (BA50) 84-lead PLCC (J83) / CLCC (Y84) [21] 100-lead TQFP (A100) [21] 100-ball Fine-Pitch BGA (BB100) for CY37064V Top Vie w 100-ball Fine-Pitch BGA (BB100) for CY37128V Top Vie w 160-Lead TQFP (A160) / CQFP (U162) for CY37128(V) and CY37256(V) 160-Lead TQFP (A160) for CY37192(V) Ultra37000 CPLD Family 208-Lead PQFP (N208) / CQFP (U208) Document #: 38-03007 Rev. *E Page 38 of 64 292-Ball PBGA (BG292) 1 2 3 4 5 6 7 8 91011121314151617181920 AGNDI/O 256-Ball Fine-Pitch BGA (BB256) 388-Lead PBGA (BG388) Top Vi ew 400-Ball Fine-Pitch BGA (BB400) J I/O59 I/O58 I/O57 I/O56 I/O55 I/O54 VCC I/O62 I/O60 I/O0I/O258 I/O202 I/O203 CLK3 /I I/O 204 I/O 205 I/O 206 I/O 207 I/O 208 I/O K GND GND GND GND I/O65 I/O64 CLK0 /I I/O63 I/O61 GND GND I/O198 I/O199 CLK2 /I Ordering Information 5.0V Ordering Information C Y 3 7 5 1 2 V P 4 0 0 - 8 3 B B X C Page Page Page Page Page 3.3V Ordering Information Page Page Page Page Page Page Page DETAILA 160-Lead Ceramic Quad Flatpack (Cavity Up) U162 Page Page BOTTOMVIEW REFERENCEJEDEC MO-192 TOPVIEW 256-Ball FBGA (17 x 17 mm) BB256 51-85108-*F Page Page Page Page Document History Page