Latched Input and Output, Asynchronous Reset | Cypress 37000 CPLD

Ultra37000 CPLD Family

Switching Waveforms (continued)

Latched Input and Output

LATCHED INPUT

LATCHED

OUTPUT

INPUT LATCH ENABLE

tICOL

tPDLL

tSL

tHL

OUTPUT LATCH ENABLE

LATCH ENABLE

tICS

tWH tWL

Asynchronous Reset

INPUT

REGISTERED

OUTPUT

CLOCK

Asynchronous Preset

tRW

tRO

tRR

INPUT

REGISTERED

OUTPUT

CLOCK

Output Enable/Disable

INPUT

OUTPUTS

tPW

tPO

tPR

tER

tEA

Document #: 38-03007 Rev. *E

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Cypress 37000 CPLD manual Latched Input and Output, Asynchronous Reset, Asynchronous Preset, Output Enable/Disable

Contents

Cypress Semiconductor Corporation FeaturesUltra37000 5.0V Devices Ultra37000V 3.3V Devices Selection Guide Logic Block Architecture Overview of Ultra37000 FamilyProgrammable Interconnect Matrix Ultra37000 Macrocell Product Term Allocator O and Buried Macrocells Timing Model Input Macrocell Jtag and PCI Standards Development Software Support Third-Party Programmers CY37064/CY37064VInput Logic Block DiagramsCY37032/CY37032V CY37192/CY37192V CY37128/CY37128V CY37256/CY37256V Logic Block Diagrams TMS CY37384/CY37384V CY37512/CY37512V Output Condition 0V Device Characteristics Maximum RatingsOperating Range2 Range Capacitance5 Endurance Characteristics53V Device Characteristics Maximum Ratings Inductance5 AC Characteristics Switching Characteristics Over the Operating Range User Option Parameters Pipelined Mode ParametersReset/Preset Parameters Parameter Description Unit Product Term Clocking Parameters Operating Frequency Parameters Reset/PresetSynchronous Product Term Combinatorial Output Switching WaveformsUser Option Jtag Timing Latched Output Latched Input Registered InputClock to Clock Latched Input and Output Asynchronous ResetAsynchronous Preset Output Enable/Disable CY37064 Power ConsumptionTypical 5.0V Power Consumption CY37032 CY37192 Typical 5.0V Power Consumption CY37128 CY37384 Typical 5.0V Power Consumption CY37256 Typical 3.3V Power Consumption CY37032V Typical 5.0V Power Consumption CY37512 CY37128V Typical 3.3V Power Consumption CY37064V CY37256V Typical 3.3V Power Consumption CY37192V CY37512V Typical 3.3V Power Consumption CY37384V Pin Plcc J67 / Clcc Y67 Top View Pin Configurations20Pin Tqfp A44 Top View Lead Plcc J83 / Clcc Y84 Top View Ball Fine-Pitch BGA BA50 Top View Lead Tqfp A100 Top View Ball Fine-Pitch BGA BB100 for CY37128V Top View Ball Fine-Pitch BGA BB100 for CY37064V Top View CLK3/I4 GND TDO I/O Lead Tqfp A160 for CY37192V Top View I/O I/O I/O I/O I/O I/O I/O I/O Lead Pqfp N208 / Cqfp U208 Top View Ball Pbga BG292 Top View Ball Fine-Pitch BGA BB256 Top View Lead Pbga BG388 Top View Ball Fine-Pitch BGA BB400 Top View 0V Ordering Information Ordering Information Lead Plastic Leaded Chip Carrier CY37064P84-154JC CY37128P84-167JC Lead Plastic Quad Flat Pack CY37256P256-154BGC 3V Ordering Information BB100 Lead Plastic Quad Flat Pack CY37256VP256-100BGC Lead Lead Pb-Free Plastic Leaded Chip Carrier J67 Package DiagramsLead Lead Pb-Free Thin Plastic Quad Flat Pack A44 Lead Ceramic Leaded Chip Carrier Y67 Lead Lead Pb-Free Plastic Leaded Chip Carrier J83 Ball 7.0 mm x 7.0 mm x 1.2 mm, 0.80 pitch Thin BGA BA48D Lead Ceramic Leaded Chip Carrier Y84 Lead Lead Pb-Free Thin Plastic Quad Flat Pack Tqfp A100 Ball Thin Ball Grid Array 11 x 11 x 1.4 mm BB100 51-85049-*B Detail a Lead Ceramic Quad Flatpack Cavity Up U162 Lead Plastic Quad Flatpack N208 Lead Ceramic Quad Flatpack Cavity Up U208 Bottom View Ball Fbga 17 x 17 mm BB256 Ball Plastic Ball Grid Array Pbga 27 x 27 x 2.33 mm BG292 Ball Plastic Ball Grid Array Pbga 35 x 35 x 2.33 mm BG388 Ball Fbga 21 x 21 x 1.4 mm BB400 3V ± Addendum 3V Operating RangeCommercial Document History Issue Orig. Description of Change Date