Cypress 37000 CPLD CY37256, CY37384

Ultra37000 CPLD Family
Document #: 38-03007 Rev. *E Page 26 of 64
CY37256
CY37384
Typical 5.0V Power Consumption (continued)
0
50
100
150
200
250
300
0 20 40 60 80 100 120 140 160 180
Frequency (MHz)
Icc (mA)
Low Power
High Speed
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 5.0V, TA = Room Temperature
0
50
100
150
200
250
300
350
400
450
500
0 20 40 60 80 100 120 140 160
Frequency (MHz)
Icc (mA)
Low Power
High Speed
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 5.0V, TA = Room Temperature
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