Bridge

VReg

This parameter is set to Disable, and the VReg will be enabled in the application code.

V Keep-alive

This parameter is set to Disable.

Watchdog Enable

This parameter should be set to Enable, but may be set to Disable for debug purposes.

5.3.2.2SPI Master User Module

The SPI Master User Module is used to communicate with the radio transceiver. The radio trans- ceiver supports leading edge data latching, non-inverted clock, and MSB first transmission as defaults. A clock divisor of 6 is chosen which generates an SPI clock of 2 MHz. The interrupt API to this module is not used.

In the PRoC RDK bridge design, the bridge implements the "3 wire" SPI; therefore, the microcontrol- ler's MISO and the radio MISO can be used as GPIOs. Also, the IRQ pin function is multiplexed onto the MOSI pin to save the GPIO pin.

5.3.2.3USB Device User Module

The USB Device User Module handles the enumeration and data transfers over USB endpoints.

5.3.2.41 Millisecond Interval Timer User Module

The 1 Millisecond Interval Timer User Module is used to determine when a USB suspend has occurred, LED on/off duration timing, RSSI checking and others.

5.3.2.5Flash Security

The bridge project within PSoC Designer has a file called FlashSecurity.txt. This file specifies access rules to blocks of the Flash ROM. Refer to the documentation listed at the top of the file for defini- tions. This file is shipped with a single change from its default configuration. The block starting at address 0x1FC0 has been changed from W: Full (Write protected) to U: Unprotected. This location of Flash has been dedicated to saving non-volatile session key for the encrypt code module and the device flag for KISSBind™.

CY4672 Reference Design Guide, Document # 001-16968 Revision **

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Cypress CY4672 manual USB Device User Module, 2.4 1 Millisecond Interval Timer User Module