CY7C1380C
CY7C1382C
Document #: 38-05237 Rev. *D Page 11 of 36
VDDQ 4,11,20,27,54,
61,70,
77
A1,A7,F1,F7,
J1,J7,M1,M7,
U1,U7
C3,C9,D3,D9,
E3,E9,
F3,F9,G3,
G9,J3,J9,
K3,K9,L3,
L9,M3,M9,N3,
N9
I/O Power Sup-
ply Power supply for the I/O circuitry.
MODE 31 R3 R1 Input-
Static Selects Burst Order. When tied to GND selects
linear burst sequence. When tied to VDD or left
floating selects interleaved burst sequence. This is
a strap pin and should remain static during device
operation. Mode Pin has an internal pull-up.
TDO - U5 P7 JTAG serial
output
Synchronous
Serial data-out to the JTAG circuit. Delivers data
on the negative edge of TCK. If the JTAG feature is
not being utilized, this pin should be left uncon-
nected. This pin is not available on TQFP
packages.
TDI - U3 P5 JTAG serial
input
Synchronous
Serial data-In to the JTAG circuit. Sampled on the
rising edge of TCK. If the JTAG feature is not being
utilized, this pin can be left floating or connected to
VDD through a pull up resistor. This pin is not avail-
able on TQFP packages.
TMS - U2 R5 JTAG serial
input
Synchronous
Serial data-In to the JTAG circuit. Sampled on the
rising edge of TCK. If the JTAG feature is not being
utilized, this pin can be disconnected or connected
to VDD. This pin is not available on TQFP packages.
TCK - U4 R7 JTAG-Clock Clock input to the JTAG circuitry. If the JTAG
feature is not being utilized, this pin must be
connected to VSS. This pin is not available on TQFP
packages.
NC 1,2,3,6,7,
14,16,25,
28,29,30,
38,39,
51,52,53,
56,57,66,
75,78,79,
95,96
B1,B7,
C1,C7,
D2,D4,
D7,E1,
E6,H2,
F2,G1,
G6,H7,
J3,J5,K1,
K6,L4,L2,L7,
M6,
N2,L7,P1,P6,
R1,
R5,R7,
T1,T4,U6
A5,B1,B4,
C1,C2,C10,D1
,D10,
E1,E10,F1,
F10,G1,
G10,H1,H3,H9
,H10,J2,J11,
K2,
K11,L2,L1,M2,
M11,
N2,N10,N5,N7
N11,P1,A1,
B11,
P2,R2
-No Connects. Not internally connected to the die.
CY7C1382C:Pin Definitions (continued)
Name TQFP BGA fBGA I/O Description
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