Ball fBGA Boundary Scan Order CY7C1382C 1M x | Cypress CY7C1380C

CY7C1380C

CY7C1382C

165-Ball fBGA Boundary Scan Order

		CY7C1382C (1M x 18)

	BIT#	BALL ID	BIT#	BALL ID

	0	B6	36	N6
	1	B7	37	R6
	2	A7	38	P6
	3	B8	39	R4
	4	A8	40	R3
	5	B9	41	P4
	6	A9	42	P3
	7	B10	43	R1
	8	A10	44	Not Bonded (Preset to 0)
	9	A11	45	Not Bonded (Preset to 0)
	10	Not Bonded (Preset to 0)	46	Not Bonded (Preset to 0)
	11	Not Bonded (Preset to 0)	47	Not Bonded (Preset to 0)
	12	Not Bonded (Preset to 0)	48	N1
	13	C11	49	M1
	14	D11	50	L1
	15	E11	51	K1
	16	F11	52	J1
	17	G11	53	Internal
	18	H11	54	G2
	19	J10	55	F2
	20	K10	56	E2
	21	L10	57	D2
	22	M10	58	Not Bonded (Preset to 0)
	23	Not Bonded (Preset to 0)	59	Not Bonded (Preset to 0)
	24	Not Bonded (Preset to 0)	60	Not Bonded (Preset to 0)
	25	Not Bonded (Preset to 0)	61	Not Bonded (Preset to 0)
	26	Not Bonded (Preset to 0)	62	Not Bonded (Preset to 0)
	27	Not Bonded (Preset to 0)	63	A2
	28	R11	64	B2
	29	R10	65	A3
	30	R9	66	B3
	31	R8	67	Not Bonded (Preset to 0)
	32	P10	68	Not Bonded (Preset to 0)
	33	P9	69	A4
	34	P8	70	B5
	35	P11	71	A6
Document #: 38-05237 Rev. *D					Page 23 of 36

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Cypress CY7C1380C manual Ball fBGA Boundary Scan Order CY7C1382C 1M x

Contents

250 MHz 225 MHz 200 MHz 167 MHz 133 MHz Unit FeaturesFunctional Description1 Selection Guide Logic Block Diagram CY7C1382C 1M x Logic Block Diagram CY7C1380C 512K x CY7C1382C 1M x Pin ConfigurationsCY7C1380C 512K X CY7C1382C 512K x NC / 72M NC / 36M NC / 72M NC / 288M Tqfp BGA CY7C1380C-Pin Definitions Address Strobe from Controller, sampled on Power supply inputs to the core of the deAddress Strobe from Processor, sampled On the rising edge of CLK, active LOW. When Serial data-out to the Jtag circuit . Delivers Power supply for the I/O circuitrySelects Burst Order . When tied to GND Ground for the I/O circuitry CY7C1382CPin Definitions Address Strobe from Processor, sampled on Rising edge of CLK, active LOW . When assertedZZ sleep Input, active High . When asserted Power supply inputs to the core of the device Serial data-out to the Jtag circuit . Delivers data Functional Overview Single Read Accesses CE2 Adsp Adsc ADV Write CLK Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics Address BWE Truth Table for Read/Write5CLK Adsp Adsc ADV Write Function CY7C1380C Ieee 1149.1 Serial Boundary Scan Jtag TAP Controller Block Diagram TAP Controller State Diagram TAP Instruction Set Bypass RegisterBoundary Scan Register Identification ID Register TAP Timing TAP AC Switching Characteristics Over the operating Range9 Parameter Description Test Conditions MIN MAX Units 3V TAP AC Test Conditions5V TAP AC Output Load Equivalent Identification Codes Identification Register DefinitionsScan Register Sizes Ball BGA Boundary Scan Order CY7C1380C 512K x Ball BGA Boundary Scan Order CY7C1382C 1M x J10 Ball fBGA Boundary Scan Order CY7C1380C 512K xA10 F10 G10 Ball fBGA Boundary Scan Order CY7C1382C 1M x Ambient Range Electrical Characteristics Over the Operating Range12Maximum Ratings Operating Range FBGA Unit Thermal Resistance14Capacitance Parameter Description Test Conditions 5V I/O Test Load AC Test Loads and Waveforms3V I/O Test Load Min Max Unit Switching Characteristics Over the Operating Range19 Read Cycle Timing21 Switching Waveforms Write Cycle Timing21 CLZ Read/Write Cycle Timing21, 23 ZZ Mode Timing 25 CY7C1382C-167AI CY7C1380C-167BGI Ordering InformationCY7C1382C-250AC CY7C1380C-250BGC Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A101 Package Diagrams Lead Pbga 14 x 22 x 2.4 mm BG119 Package Diagrams REV ECN no Issue Date Orig. Description of ChangeDocument History