Cypress CY7C1380C, CY7C1382C Switching Waveforms

CY7C1380C

CY7C1382C

Document #: 38-05237 Rev. *D Page 28 of 36

Switching Waveforms

Read Cycle Timing[21]

Notes:

21.On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

22.Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW.

tCYC

tCL

CLK

ADSP

tADH

tADS

ADDRESS

tCH

ADSC

tAH

tAS

tCEH

tCES

GW, BWE,

BWx

ata Out (Q) High-Z

tCLZ

tDOH

tCO

ADV

tOEHZ

tCO

Single READ BURST READ

tOEV

tOELZ tCHZ

ADV

suspends

burst.

Burst wraps around

to its initial state

tADVH

tADVS

tWEH

tWES

tADH

tADS

Q(A2) Q(A2 + 1) Q(A2 + 2)

Q(A1) Q(A2) Q(A2 + 1)Q(A2 + 3)

A2 A3

Deselect

cycle

Burst continued with

new base address

DON’T CARE UNDEFINED

[+] Feedback

Contents

Main 18-Mb (512K x 36/1M x 18) Pipelined SRAM CY7C1380C CY7C1382C Features Functional Description Selection Guide CY7C1382C Document #: 38-05237 Rev. *D Page 2 of 36 Logic Block Diagram CY7C1380C (512K x 36) WRITE DRIVER WRITE DRIVER CY7C1380C CY7C1382C Document #: 38-05237 Rev. *D Page 3 of 36 Pin Configurations CY7C1380C (512K X 36) CY7C1382C (1M x 18) Pin Configurations 119-ball BGA (1 Chip Enable with JTAG) Pin Configurations 165-ball fBGA 2345671 A B C D E F G H J K L M N P R 891011 2345671 A B C D E F G H J K L M N P R CY7C1380CPin Definitions CY7C1380C CY7C1382C CY7C1380CPin Definitions CY7C1380C CY7C1382C CY7C1380CPin Definitions Page Page CY7C1382C:Pin Definitions Functional Overview CY7C1380C CY7C1382C Interleaved Burst Address Table (MODE = Floating or VDD) Linear Burst Address Table (MODE = GND) ZZ Mode Electrical Characteristics Truth Table Truth Table for Read/Write Truth Table IEEE 1149.1 Serial Boundary Scan (JTAG) TAP Controller State Diagram TAP Controller Block Diagram Page TAP Timing TAP AC Switching Characteristics Over the operating Range[9, 10] 3.3V TAP AC Test Conditions 3.3V TAP AC Output Load Equivalent F DO T Identification Register Definitions Scan Register Sizes Identification Codes 119-Ball BGA Boundary Scan Order CY7C1380C (512K x 36) CY7C1382C (1M x 18) 119-Ball BGA Boundary Scan Order 165-Ball fBGA Boundary Scan Order CY7C1380C (512K x 36) CY7C1382C (1M x 18) 165-Ball fBGA Boundary Scan Order Maximum Ratings Operating Range Electrical Characteristics Thermal Resistance Capacitance AC Test Loads and Waveforms = 1.5V (c) (a) (b) V Switching Characteristics Switching Waveforms Read Cycle Timing Write Cycle Timing Read/Write Cycle Timing Z Z Mode Timing Ordering Information Package Diagrams DIMENSIONSARE IN MILLIMETERS. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101 51-85050-*A Page Page Document History Page