Switching Waveforms, Read Cycle Timing21 | Cypress CY7C1382C

CY7C1380C

CY7C1382C

Switching Waveforms

Read Cycle Timing[21]

tCYC

CLK

tCH

tADS tADH

ADSP

ADSC

tAS tAH

tCL

tADS tADH

ADDRESS

GW, BWE, BWx

CE

ADV

OE

Data Out (Q)

A1	A2	A3
tWES	tWEH	Burst continued with
tWES	tWEH	new base address
tCES tCEH		Deselect
tCES tCEH		cycle

tADVS tADVH

ADV suspends burst.

		tOEV	tCO
	tOEHZ	tOELZ	tDOH					tCHZ
	tCLZ
High-Z	Q(A1)		Q(A2)	Q(A2 + 1)	Q(A2 + 2)	Q(A2 + 3)	Q(A2)	Q(A2 + 1)
	tCO
							Burst wraps around
							to its initial state
	Single READ				BURST READ
			DON’T CARE		UNDEFINED

Notes:

21.On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

22.Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW.

Document #: 38-05237 Rev. *D

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Cypress CY7C1382C, CY7C1380C manual Switching Waveforms, Read Cycle Timing21

Contents

Features Functional Description1Selection Guide 250 MHz 225 MHz 200 MHz 167 MHz 133 MHz Unit Logic Block Diagram CY7C1380C 512K x Logic Block Diagram CY7C1382C 1M x CY7C1380C 512K X Pin ConfigurationsCY7C1382C 1M x NC / 72M NC / 36M CY7C1382C 512K x NC / 288M NC / 72M CY7C1380C-Pin Definitions Tqfp BGA Power supply inputs to the core of the de Address Strobe from Processor, sampledOn the rising edge of CLK, active LOW. When Address Strobe from Controller, sampled on Power supply for the I/O circuitry Selects Burst Order . When tied to GNDGround for the I/O circuitry Serial data-out to the Jtag circuit . Delivers CY7C1382CPin Definitions Rising edge of CLK, active LOW . When asserted ZZ sleep Input, active High . When assertedPower supply inputs to the core of the device Address Strobe from Processor, sampled on Serial data-out to the Jtag circuit . Delivers data Single Read Accesses Functional Overview Interleaved Burst Address Table Mode = Floating or VDD ZZ Mode Electrical CharacteristicsAddress CE2 Adsp Adsc ADV Write CLK Truth Table for Read/Write5 CLK Adsp Adsc ADV WriteFunction CY7C1380C BWE TAP Controller Block Diagram TAP Controller State Diagram Ieee 1149.1 Serial Boundary Scan Jtag Bypass Register Boundary Scan RegisterIdentification ID Register TAP Instruction Set TAP AC Switching Characteristics Over the operating Range9 TAP Timing 5V TAP AC Output Load Equivalent 3V TAP AC Test ConditionsParameter Description Test Conditions MIN MAX Units Scan Register Sizes Identification Register DefinitionsIdentification Codes Ball BGA Boundary Scan Order CY7C1380C 512K x Ball BGA Boundary Scan Order CY7C1382C 1M x Ball fBGA Boundary Scan Order CY7C1380C 512K x A10F10 G10 J10 Ball fBGA Boundary Scan Order CY7C1382C 1M x Electrical Characteristics Over the Operating Range12 Maximum RatingsOperating Range Ambient Range Thermal Resistance14 CapacitanceParameter Description Test Conditions FBGA Unit 3V I/O Test Load AC Test Loads and Waveforms5V I/O Test Load Switching Characteristics Over the Operating Range19 Min Max Unit Switching Waveforms Read Cycle Timing21 Write Cycle Timing21 Read/Write Cycle Timing21, 23 CLZ ZZ Mode Timing 25 CY7C1382C-250AC CY7C1380C-250BGC Ordering InformationCY7C1382C-167AI CY7C1380C-167BGI Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A101 Lead Pbga 14 x 22 x 2.4 mm BG119 Package Diagrams Document History Issue Date Orig. Description of ChangeREV ECN no