Cypress CY7C1382C, CY7C1380C Ground for the I/O circuitry, Power supply for the I/O circuitry

					CY7C1380C
					CY7C1382C
CY7C1380C–Pin Definitions (continued)
Name	TQFP	BGA	fBGA	I/O	Description
VSSQ	5,10,21,26,55,	-	-	I/O Ground	Ground for the I/O circuitry.
	60,71,
	76
VDDQ	4,11,20,27,54,	A1,F1,J1,M1,	C3,C9,D3,D9,	I/O Power	Power supply for the I/O circuitry.
	61,70,	U1,	E3,E9,F3,F9,G	Supply
	77	A7,F7,J7,M7,	3,
		U7	G9,J3,J9,
			K3,K9,L3,
			L9,M3,M9,N3,
			N9
MODE	31	R3	R1	Input-	Selects Burst Order. When tied to GND
				Static	selects linear burst sequence. When tied to VDD
					or left floating selects interleaved burst
					sequence. This is a strap pin and should remain
					static during device operation. Mode Pin has an
					internal pull-up.
TDO	-	U5	P7	JTAG serial	Serial data-out to the JTAG circuit. Delivers
				output	data on the negative edge of TCK. If the JTAG
				Synchronous	feature is not being utilized, this pin should be
					disconnected. This pin is not available on TQFP
					packages.
TDI	-	U3	P5	JTAG serial	Serial data-In to the JTAG circuit. Sampled
				input	on the rising edge of TCK. If the JTAG feature
				Synchronous	is not being utilized, this pin can be discon-
					nected or connected to VDD. This pin is not
					available on TQFP packages.
TMS	-	U2	R5	JTAG serial	Serial data-In to the JTAG circuit. Sampled
				input	on the rising edge of TCK. If the JTAG feature
				Synchronous	is not being utilized, this pin can be discon-
					nected or connected to VDD. This pin is not
					available on TQFP packages.
TCK	-	U4	R7	JTAG-Clock	Clock input to the JTAG circuitry. If the JTAG
					feature is not being utilized, this pin must be
					connected to VSS. This pin is not available on
					TQFP packages.
NC	14,16,66,	B1,C1,	A11,B1,C2,C1	-	No Connects. Not internally connected to the
	39,38	R1,T1,T2,J3,	0,H1,H3,H9,		die
		D4,	H10,
		L4,J5,R5,6T,	N2,N5,N7,N10
		6U,	,P1,A1,B11,P2
		B7,C7,	,R2,N6
		R7

Document #: 38-05237 Rev. *D Page 8 of 36

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