Cypress CY7C1380C manual TAP Timing, TAP AC Switching Characteristics Over the operating Range9

CY7C1380C

CY7C1382C

Note that since the PRELOAD part of the command is not implemented, putting the TAP to the Update-DR state while performing a SAMPLE/PRELOAD instruction will have the same effect as the Pause-DR command.

BYPASS

When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass

register is placed between the TDI and TDO balls. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board.

Reserved

These instructions are not implemented but are reserved for future use. Do not use these instructions.

TAP Timing

12

Test Clock

(TCK)tTH

tTMSS tTMSH

Test Mode Select (TMS)

tTDIS tTDIH

Test Data-In (TDI)

3 4 5 6

tTL tCYC

tTDOV

tTDOX

Test Data-Out
(TDO)
DON’T CARE	UNDEFINED

TAP AC Switching Characteristics Over the operating Range[9, 10]

Parameter	Symbol	Min	Max	Units
Clock
TCK Clock Cycle Time	tTCYC	100		ns
TCK Clock Frequency	tTF		10	MHz
TCK Clock HIGH time	tTH	40		ns
TCK Clock LOW time	tTL	40		ns
Output Times
TCK Clock LOW to TDO Valid	tTDOV		20	ns
TCK Clock LOW to TDO Invalid	tTDOX	0		ns
Setup Times
TMS Set-Up to TCK Clock Rise	tTMSS	10		ns
TDI Set-Up to TCK Clock Rise	tTDIS	10		ns
Capture Set-Up to TCK Rise	tCS	10
Hold Times
TMS hold after TCK Clock Rise	tTMSH	10		ns
TDI Hold after Clock Rise	tTDIH	10		ns
Capture Hold after Clock Rise	tCH	10		ns

Notes:

9.tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.

10. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1ns.

Document #: 38-05237 Rev. *D Page 17 of 36

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