CY7C1380C

CY7C1382C

Asserting ADV LOW at clock rise will automatically increment the burst counter to the next address in the burst sequence. Both Read and Write burst operations are supported.

Interleaved Burst Address Table (MODE = Floating or VDD)

First

Second

Third

Fourth

Address

Address

Address

Address

A1: A0

A1: A0

A1: A0

A1: A0

00

01

10

11

 

 

 

 

01

00

11

10

 

 

 

 

10

11

00

01

 

 

 

 

11

10

01

00

 

 

 

 

Linear Burst

Address

Table

 

(MODE = GND)

 

 

First

Second

Third

Fourth

Address

Address

Address

Address

A1: A0

A1: A0

A1: A0

A1: A0

00

01

10

11

 

 

 

 

01

10

11

00

 

 

 

 

10

11

00

01

 

 

 

 

11

00

01

10

 

 

 

 

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering

the “sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW

.

ZZ Mode Electrical Characteristics

 

Parameter

 

Description

 

 

 

 

 

 

 

Test Conditions

 

 

 

Min.

 

 

Max.

 

Unit

 

IDDZZ

 

Snooze mode standby current

 

 

 

ZZ > VDD – 0.2V

 

 

 

 

 

 

 

 

 

 

 

60mA

 

mA

 

tZZS

 

Device operation to ZZ

 

 

 

 

 

ZZ > VDD – 0.2V

 

 

 

 

 

 

 

 

 

 

 

2tCYC

 

ns

 

tZZREC

 

ZZ recovery time

 

 

 

 

 

ZZ < 0.2V

 

 

 

 

 

 

2tCYC

 

 

 

 

 

 

ns

 

tZZI

 

ZZ Active to snooze current

 

 

 

 

 

This parameter is sampled

 

 

 

 

 

 

 

 

2tCYC

 

ns

 

tRZZI

 

ZZ Inactive to exit snooze current

 

 

 

This parameter is sampled

 

 

0

 

 

 

 

 

 

 

ns

 

Truth Table[ 3, 4, 5, 6, 7, 8]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Operation

Add. Used

 

CE

1

CE2

 

CE

3

ZZ

 

ADSP

 

 

ADSC

 

 

ADV

 

 

WRITE

 

 

 

OE

 

CLK

DQ

 

Deselect Cycle,Power Down

None

 

H

X

 

X

L

 

X

 

L

 

X

 

 

X

 

X

 

L-H

Tri-State

 

Deselect Cycle,Power Down

None

 

L

L

 

X

L

 

L

 

X

 

X

 

 

X

 

X

 

L-H

Tri-State

 

Deselect Cycle,Power Down

None

 

L

X

 

H

L

 

L

 

X

 

X

 

 

X

 

X

 

L-H

Tri-State

 

Deselect Cycle,Power Down

None

 

L

L

 

X

L

 

H

 

L

 

X

 

 

X

 

X

 

L-H

Tri-State

 

Deselect Cycle,Power Down

None

 

L

X

 

H

L

 

H

 

L

 

X

 

 

X

 

X

 

L-H

Tri-State

 

Snooze Mode,Power Down

None

 

X

X

 

X

H

 

X

 

X

 

X

 

 

X

 

X

 

X

Tri-State

 

READ Cycle, Begin Burst

External

 

L

H

 

L

L

 

L

 

X

 

X

 

 

X

 

L

 

L-H

Q

 

READ Cycle, Begin Burst

External

 

L

H

 

L

L

 

L

 

X

 

X

 

 

X

 

H

 

L-H

Tri-State

 

WRITE Cycle, Begin Burst

External

 

L

H

 

L

L

 

H

 

L

 

X

 

 

L

 

X

 

L-H

D

 

READ Cycle, Begin Burst

External

 

L

H

 

L

L

 

H

 

L

 

X

 

 

H

 

L

 

L-H

Q

 

READ Cycle, Begin Burst

External

 

L

H

 

L

L

 

H

 

L

 

X

 

 

H

 

H

 

L-H

Tri-State

 

READ Cycle, Continue Burst

Next

 

X

X

 

X

L

 

H

 

H

 

L

 

 

H

 

L

 

L-H

Q

 

READ Cycle, Continue Burst

Next

 

X

X

 

X

L

 

H

 

H

 

L

 

 

H

 

H

 

L-H

Tri-State

 

READ Cycle, Continue Burst

Next

 

H

X

 

X

L

 

X

 

H

 

L

 

 

H

 

L

 

L-H

Q

Document #: 38-05237 Rev. *D

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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Cypress CY7C1380C, CY7C1382C Interleaved Burst Address Table Mode = Floating or VDD, ZZ Mode Electrical Characteristics