Cypress CY7C1380C, CY7C1382C Ordering Information

CY7C1380C

CY7C1382C

Document #: 38-05237 Rev. *D Page 32 of 36

Ordering Information

Speed

(MHz) Ordering Code Package

Name Part and Package Type Operating

Range

250 CY7C1380C-250AC

CY7C1382C-250AC A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm) Commercial

CY7C1380C-250BGC

CY7C1382C-250BGC BG119 119 PBG A

CY7C1380C-250BZC

CY7C1382C-250BZC BB165A 165 fBGA

225 CY7C1380C-225AC A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)

CY7C1382C-225AC

CY7C1380C-225BGC

CY7C1382C-225BGC BG119 119 PBG A

CY7C1380C-225BZC

CY7C1382C-225BZC BB165A 165 fBGA

200 CY7C1380C-200AC

CY7C1382C-200AC A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)

CY7C1380C-200BGC BG119 119 PBG A

CY7C1382C-200BGC

CY7C1380C-200BZC BB165A 165 fBGA

CY7C1382C-200BZC

167 CY7C1380C-167AC

CY7C1382C-167AC A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)

CY7C1380C-167BGC BG119 119 PBG A

CY7C1382C-167BGC

CY7C1380C-167BZC

CY7C1382C-167BZC BB165A 165 fBGA

133 CY7C1380C-133AC A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)

167 CY7C1380C-167AI

CY7C1382C-167AI A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm) Industrial

CY7C1380C-167BGI

CY7C1382C-167BGI BG119 119 PBG A

CY7C1380C-167BZI BB165A 165 fBGA

CY7C1382C-167BZI

Shaded areas contain advance information.

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Contents

Main 18-Mb (512K x 36/1M x 18) Pipelined SRAM CY7C1380C CY7C1382C Features Functional Description Selection Guide CY7C1382C Document #: 38-05237 Rev. *D Page 2 of 36 Logic Block Diagram CY7C1380C (512K x 36) WRITE DRIVER WRITE DRIVER CY7C1380C CY7C1382C Document #: 38-05237 Rev. *D Page 3 of 36 Pin Configurations CY7C1380C (512K X 36) CY7C1382C (1M x 18) Pin Configurations 119-ball BGA (1 Chip Enable with JTAG) Pin Configurations 165-ball fBGA 2345671 A B C D E F G H J K L M N P R 891011 2345671 A B C D E F G H J K L M N P R CY7C1380CPin Definitions CY7C1380C CY7C1382C CY7C1380CPin Definitions CY7C1380C CY7C1382C CY7C1380CPin Definitions Page Page CY7C1382C:Pin Definitions Functional Overview CY7C1380C CY7C1382C Interleaved Burst Address Table (MODE = Floating or VDD) Linear Burst Address Table (MODE = GND) ZZ Mode Electrical Characteristics Truth Table Truth Table for Read/Write Truth Table IEEE 1149.1 Serial Boundary Scan (JTAG) TAP Controller State Diagram TAP Controller Block Diagram Page TAP Timing TAP AC Switching Characteristics Over the operating Range[9, 10] 3.3V TAP AC Test Conditions 3.3V TAP AC Output Load Equivalent F DO T Identification Register Definitions Scan Register Sizes Identification Codes 119-Ball BGA Boundary Scan Order CY7C1380C (512K x 36) CY7C1382C (1M x 18) 119-Ball BGA Boundary Scan Order 165-Ball fBGA Boundary Scan Order CY7C1380C (512K x 36) CY7C1382C (1M x 18) 165-Ball fBGA Boundary Scan Order Maximum Ratings Operating Range Electrical Characteristics Thermal Resistance Capacitance AC Test Loads and Waveforms = 1.5V (c) (a) (b) V Switching Characteristics Switching Waveforms Read Cycle Timing Write Cycle Timing Read/Write Cycle Timing Z Z Mode Timing Ordering Information Package Diagrams DIMENSIONSARE IN MILLIMETERS. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101 51-85050-*A Page Page Document History Page