Cypress CY7C1380C Address Strobe from Processor, sampled, Rising edge of CLK, active LOW. When

									CY7C1380C
									CY7C1382C
	CY7C1380C–Pin Definitions (continued)
		Name	TQFP	BGA	fBGA	I/O			Description
			84	A4	B9	Input-	Address Strobe from Processor, sampled
		ADSP
						Synchronous	on the rising edge of CLK, active LOW. When
							asserted LOW, addresses presented to the
							device are captured in the address registers.
							A1: A0 are also loaded into the burst counter.
							When	ADSP	and ADSC are both asserted, only
							ADSP is recognized. ASDP is ignored when
							CE1 is deasserted HIGH.
			85	B4	A8	Input-	Address Strobe from Controller, sampled on
		ADSC
						Synchronous	the rising edge of CLK, active LOW. When
							asserted LOW, addresses presented to the
							device are captured in the address registers.
							A1: A0 are also loaded into the burst counter.
							When	ADSP	and ADSC are both asserted, only
							ADSP is recognized.
		ZZ	64	T7	H11	Input-	ZZ “sleep” Input, active HIGH. When
						Asynchronous	asserted HIGH places the device in a
							non-time-critical “sleep” condition with data
							integrity preserved. For normal operation, this
							pin has to be LOW or left floating. ZZ pin has an
							internal pull-down.
		DQs, DQPs	52,53,56,	K6,L6,	M11,L11,	I/O-	Bidirectional Data I/O lines. As inputs, they
			57,58,59,	M6,N6,	K11,J11,	Synchronous	feed into an on-chip data register that is
			62,63,68,	K7,L7,	J10,K10,		triggered by the rising edge of CLK. As outputs,
			69,72,73,	N7,P7,	L10,M10,		they deliver the data contained in the memory
			74,75,78,	E6,F6,	D10,E10,		location specified by the addresses presented
			79,2,3,6,7,8,9,	G6,H6,	F10,G10,		during the previous clock rise of the read cycle.
			12,13,18,19,22	D7,E7,	D11,E11,		The direction of the pins is controlled by OE.
			,	G7,H7,	F11,G11,		When OE is asserted LOW, the pins behave as
			23,24,25,	D1,E1,	D1,E1,F1,		outputs. When HIGH, DQs and DQPX are
			28,29,51,	G1,H1,	G1,D2,E2,F2,		placed in a tri-state condition.
			80,1,30	E2,F2,	G2,J1,
				G2,H2,	K1,L1,M1,
				K1,L1,	J2,K2,L2,
				N1,P1,	M2,N11,
				K2,L2,	C11,C1,N1
				M2,N2,
				P6,D6,
				D2,P2
		VDD	15,41,65,	J2,C4,J4,R4,	D4,D8,E4,E8,	Power Supply	Power supply inputs to the core of the de-
			91	J6	F4,F8,		vice.
					G4,G8,H4,H8,
					J4,J8,
					K4,K8,L4,
					L8,M4,M8
		VSS	17,40,67,	D3,E3,	C4,C5,C6,C7,	Ground	Ground for the core of the device.
			90	F3,H3,	C8,D5,D6,D7,
				K3,M3,	E5,E6,E7,F5,
				N3,P3,	F6,F7,G5,G6,
				D5,E5,	G7,H2,H5,H6,
				F5,H5,	H7,J5,J6,J7,
				K5,M5,	K5,K6,K7,
				N5,P5	L5,L6,L7,
					M5,M6,M7,N4,
					N8
Document #: 38-05237 Rev. *D									Page 7 of 36

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