CY7C1380C
CY7C1382C
Document #: 38-05237 Rev. *D Page 25 of 36
ISB3 Automatic CE
Power-down
Current—CMOS Inputs
VDD = Max, Device Deselected, or
VIN ≤ 0.3V or VIN > VDDQ – 0.3V
f = fMAX = 1/tCYC
4.0-ns cycle, 250 MHz 105 mA
4.4-ns cycle, 225 MHz 100 mA
5.0-ns cycle, 200 MHz 95 mA
6.0-ns cycle, 167 MHz 85 mA
7.5-ns cycle, 133 MHz 80 mA
ISB4 Automatic CE
Power-down
Current—TTL Inputs
VDD = Max, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL, f = 0 All speeds 80 mA
Shaded areas contain advance information.
Notes:
12.Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > -2V (Pulse width less than tCYC/2).
13.TPower-up: Assumes a linear ramp from 0v to VDD(min.) within 200ms. During this time VIH < VDD and VDDQ < VDD\
Thermal Resistance[14]
Parameter Description Test Conditions TQFP
Package BGA
Package fBGA
Package Unit
ΘJA Thermal Resistance
(Junction to Ambient) Test conditions follow standard
test methods and procedures
for measuring thermal
impedence, per EIA / JESD51.
31 45 46 °C/W
ΘJC Thermal Resistance
(Junction to Case) 6 7 3 °C/W
Capacitance[14]
Parameter Description Test Conditions TQFP
Package BGA
Package fBGA
Package Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz,
VDD = 3.3V.
VDDQ = 2.5V
5 8 9 pF
CCLK Clock Input Capacitance 5 8 9 pF
CI/O Input/Output Capacitance 5 8 9 pF
Notes:
14.Tested initially and after any design or process change that may affect these parameters
Electrical Characteristics Over the Operating Range[12, 13] (continued)
Parameter Description Test Conditions Min. Max. Unit
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