Cypress CY7C1380C manual Thermal Resistance14, Capacitance, Parameter Description Test Conditions

CY7C1380C

CY7C1382C

Electrical Characteristics Over the Operating Range[12, 13] (continued)

Parameter	Description	Test Conditions		Min.	Max.	Unit
ISB3	Automatic CE	VDD = Max, Device Deselected, or	4.0-ns cycle, 250 MHz		105	mA
	Power-down	VIN ≤ 0.3V or VIN > VDDQ – 0.3V	4.4-ns cycle, 225 MHz		100	mA
	Current—CMOS Inputs	f = fMAX = 1/tCYC
			5.0-ns cycle, 200 MHz		95	mA
			6.0-ns cycle, 167 MHz		85	mA
			7.5-ns cycle, 133 MHz		80	mA
ISB4	Automatic CE	VDD = Max, Device Deselected,	All speeds		80	mA
	Power-down	VIN ≥ VIH or VIN ≤ VIL, f = 0
	Current—TTL Inputs

Shaded areas contain advance information.

Notes:

12.Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > -2V (Pulse width less than tCYC/2).

13.TPower-up: Assumes a linear ramp from 0v to VDD(min.) within 200ms. During this time VIH < VDD and VDDQ < VDD\

Thermal Resistance[14]

	Parameter	Description		Test Conditions	TQFP	BGA	fBGA	Unit
					Package	Package	Package
	ΘJA	Thermal Resistance	Test conditions follow standard		31	45	46	°C/W
		(Junction to Ambient)	test methods and procedures
			for measuring thermal
	ΘJC	Thermal Resistance			6	7	3	°C/W
			impedence, per EIA / JESD51.
		(Junction to Case)
Capacitance[14]
	Parameter	Description		Test Conditions	TQFP	BGA	fBGA	Unit
					Package	Package	Package
	CIN	Input Capacitance		TA = 25°C, f = 1 MHz,	5	8	9	pF
				VDD = 3.3V.
	CCLK	Clock Input Capacitance			5	8	9	pF
				VDDQ = 2.5V
	CI/O	Input/Output Capacitance			5	8	9	pF

Notes:

14. Tested initially and after any design or process change that may affect these parameters

Document #: 38-05237 Rev. *D Page 25 of 36

[+] Feedback