Write Cycle Timing21 | Cypress CY7C1380C, CY7C1382C guide

CY7C1380C

CY7C1382C

Switching Waveforms (continued)

Write Cycle Timing[21, 22]

tCYC

CLK

tCH

tCL

tADS

tADH

ADSP

tADS

tADH

ADSC extends burst

tADS

tADH

ADSC

tAS

tAH

ADDRESS

Byte write signals are

ignored for first cycle when

tWES tWEH

ADSP initiates burst

BWE,

BWX

tWES tWEH

tCES

tCEH

tADVS tADVH

ADV

ADV suspends burst

tDS

tDH

Data In (D)

High-Z

D(A1)

D(A2)

D(A2 + 1)

D(A2 + 2)

D(A2 + 3)

D(A3)

D(A3 + 1)

D(A3 + 2)

OEHZ

Data Out (Q)

BURST READ

Single WRITE

	BURST WRITE
DON’T CARE	UNDEFINED

Extended BURST WRITE

Document #: 38-05237 Rev. *D

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Cypress CY7C1380C, CY7C1382C manual Write Cycle Timing21

Contents

Functional Description1 FeaturesSelection Guide 250 MHz 225 MHz 200 MHz 167 MHz 133 MHz Unit Logic Block Diagram CY7C1382C 1M x Logic Block Diagram CY7C1380C 512K x CY7C1382C 1M x Pin ConfigurationsCY7C1380C 512K X CY7C1382C 512K x NC / 72M NC / 36M NC / 72M NC / 288M Tqfp BGA CY7C1380C-Pin Definitions Address Strobe from Processor, sampled Power supply inputs to the core of the deOn the rising edge of CLK, active LOW. When Address Strobe from Controller, sampled on Selects Burst Order . When tied to GND Power supply for the I/O circuitryGround for the I/O circuitry Serial data-out to the Jtag circuit . Delivers CY7C1382CPin Definitions ZZ sleep Input, active High . When asserted Rising edge of CLK, active LOW . When assertedPower supply inputs to the core of the device Address Strobe from Processor, sampled on Serial data-out to the Jtag circuit . Delivers data Functional Overview Single Read Accesses ZZ Mode Electrical Characteristics Interleaved Burst Address Table Mode = Floating or VDDAddress CE2 Adsp Adsc ADV Write CLK CLK Adsp Adsc ADV Write Truth Table for Read/Write5Function CY7C1380C BWE Ieee 1149.1 Serial Boundary Scan Jtag TAP Controller Block Diagram TAP Controller State Diagram Boundary Scan Register Bypass RegisterIdentification ID Register TAP Instruction Set TAP Timing TAP AC Switching Characteristics Over the operating Range9 Parameter Description Test Conditions MIN MAX Units 3V TAP AC Test Conditions5V TAP AC Output Load Equivalent Identification Codes Identification Register DefinitionsScan Register Sizes Ball BGA Boundary Scan Order CY7C1380C 512K x Ball BGA Boundary Scan Order CY7C1382C 1M x A10 Ball fBGA Boundary Scan Order CY7C1380C 512K xF10 G10 J10 Ball fBGA Boundary Scan Order CY7C1382C 1M x Maximum Ratings Electrical Characteristics Over the Operating Range12Operating Range Ambient Range Capacitance Thermal Resistance14Parameter Description Test Conditions FBGA Unit 5V I/O Test Load AC Test Loads and Waveforms3V I/O Test Load Min Max Unit Switching Characteristics Over the Operating Range19 Read Cycle Timing21 Switching Waveforms Write Cycle Timing21 CLZ Read/Write Cycle Timing21, 23 ZZ Mode Timing 25 CY7C1382C-167AI CY7C1380C-167BGI Ordering InformationCY7C1382C-250AC CY7C1380C-250BGC Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A101 Package Diagrams Lead Pbga 14 x 22 x 2.4 mm BG119 Package Diagrams REV ECN no Issue Date Orig. Description of ChangeDocument History