Ball BGA Boundary Scan Order CY7C1380C 512K x | Cypress CY7C1382C

CY7C1380C

CY7C1382C

119-Ball BGA Boundary Scan Order

		CY7C1380C (512K x 36)

BIT#	BALL ID		BIT#		BALL ID

1	K4		37		B2
2	H4		38		P4
3	M4		39		N4
4	F4		40		R6
5	B4		41		T5
6	A4		42		T3
7	G4		43		R2
8	C6		44		R3
9	A6		45		P2
10	D6		46		P1
11	D7		47		N2
12	E6		48		L2
13	G6		49		K1
14	H7		50		N1
15	E7		51		M2
16	F6		52		L1
17	G7		53		K2
18	H6		54		Not Bonded (Preset to 1)
19	T7		55		H1
20	K7		56		G2
21	L6		57		E2
22	N6		58		D1
23	P7		59		H2
24	K6		60		G1
25	L7		61		F2
26	M6		62		E1
27	N7		63		D2
28	P6		64		A5
29	B5		65		A3
30	B3		66		E4
31	C5		67		Internal
32	C3		68		L3
33	C2		69		G3
34	A2		70		G5
35	T4		71		L5
36	B6		72		Internal
Document #: 38-05237 Rev. *D							Page 20 of 36

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Cypress CY7C1382C manual Ball BGA Boundary Scan Order CY7C1380C 512K x

Contents

Features Functional Description1Selection Guide 250 MHz 225 MHz 200 MHz 167 MHz 133 MHz Unit Logic Block Diagram CY7C1380C 512K x Logic Block Diagram CY7C1382C 1M x CY7C1382C 1M x Pin ConfigurationsCY7C1380C 512K X NC / 72M NC / 36M CY7C1382C 512K x NC / 288M NC / 72M CY7C1380C-Pin Definitions Tqfp BGA Power supply inputs to the core of the de Address Strobe from Processor, sampledOn the rising edge of CLK, active LOW. When Address Strobe from Controller, sampled on Power supply for the I/O circuitry Selects Burst Order . When tied to GNDGround for the I/O circuitry Serial data-out to the Jtag circuit . Delivers CY7C1382CPin Definitions Rising edge of CLK, active LOW . When asserted ZZ sleep Input, active High . When assertedPower supply inputs to the core of the device Address Strobe from Processor, sampled on Serial data-out to the Jtag circuit . Delivers data Single Read Accesses Functional Overview Interleaved Burst Address Table Mode = Floating or VDD ZZ Mode Electrical CharacteristicsAddress CE2 Adsp Adsc ADV Write CLK Truth Table for Read/Write5 CLK Adsp Adsc ADV WriteFunction CY7C1380C BWE TAP Controller Block Diagram TAP Controller State Diagram Ieee 1149.1 Serial Boundary Scan Jtag Bypass Register Boundary Scan RegisterIdentification ID Register TAP Instruction Set TAP AC Switching Characteristics Over the operating Range9 TAP Timing Parameter Description Test Conditions MIN MAX Units 3V TAP AC Test Conditions5V TAP AC Output Load Equivalent Identification Codes Identification Register DefinitionsScan Register Sizes Ball BGA Boundary Scan Order CY7C1380C 512K x Ball BGA Boundary Scan Order CY7C1382C 1M x Ball fBGA Boundary Scan Order CY7C1380C 512K x A10F10 G10 J10 Ball fBGA Boundary Scan Order CY7C1382C 1M x Electrical Characteristics Over the Operating Range12 Maximum RatingsOperating Range Ambient Range Thermal Resistance14 CapacitanceParameter Description Test Conditions FBGA Unit 5V I/O Test Load AC Test Loads and Waveforms3V I/O Test Load Switching Characteristics Over the Operating Range19 Min Max Unit Switching Waveforms Read Cycle Timing21 Write Cycle Timing21 Read/Write Cycle Timing21, 23 CLZ ZZ Mode Timing 25 CY7C1382C-167AI CY7C1380C-167BGI Ordering InformationCY7C1382C-250AC CY7C1380C-250BGC Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A101 Lead Pbga 14 x 22 x 2.4 mm BG119 Package Diagrams REV ECN no Issue Date Orig. Description of ChangeDocument History