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Cypress CY7C1382C manual Ball fBGA Boundary Scan Order CY7C1380C 512K x, A10, F10 G10, J10, M10

Models: CY7C1380C CY7C1382C

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CY7C1380C

CY7C1382C

165-Ball fBGA Boundary Scan Order

		CY7C1380C (512K x 36)

	BIT#	BALL ID	BIT#		BALL ID

	1	B6	37		N6
	2	B7	38		R6
	3	A7	39		P6
	4	B8	40		R4
	5	A8	41		R3
	6	B9	42		P4
	7	A9	43		P3
	8	B10	44		R1
	9	A10	45		N1
	10	C11	46		L2
	11	E10	47		K2
	12	F10	48		J2
	13	G10	49		M2
	14	D10	50		M1
	15	D11	51		L1
	16	E11	52		K1
	17	F11	53		J1
	18	G11	54		Internal
	19	H11	55		G2
	20	J10	56		F2
	21	K10	57		E2
	22	L10	58		D2
	23	M10	59		G1
	24	J11	60		F1
	25	K11	61		E1
	26	L11	62		D1
	27	M11	63		C1
	28	N11	64		A2
	29	R11	65		B2
	30	R10	66		A3
	31	R9	67		B3
	32	R8	68		B4
	33	P10	69		A4
	34	P9	70		A5
	35	P8	71		B5
	36	P11	72		A6
Document #: 38-05237 Rev. *D						Page 22 of 36

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Cypress CY7C1382C manual Ball fBGA Boundary Scan Order CY7C1380C 512K x, A10, F10 G10, J10, M10

Contents

Selection Guide FeaturesFunctional Description1 250 MHz 225 MHz 200 MHz 167 MHz 133 MHz UnitLogic Block Diagram CY7C1380C 512K x Logic Block Diagram CY7C1382C 1M xCY7C1380C 512K X Pin ConfigurationsCY7C1382C 1M x NC / 72M NC / 36M CY7C1382C 512K xNC / 288M NC / 72MCY7C1380C-Pin Definitions Tqfp BGAOn the rising edge of CLK, active LOW. When Power supply inputs to the core of the deAddress Strobe from Processor, sampled Address Strobe from Controller, sampled onGround for the I/O circuitry Power supply for the I/O circuitrySelects Burst Order . When tied to GND Serial data-out to the Jtag circuit . DeliversCY7C1382CPin Definitions Power supply inputs to the core of the device Rising edge of CLK, active LOW . When assertedZZ sleep Input, active High . When asserted Address Strobe from Processor, sampled onSerial data-out to the Jtag circuit . Delivers data Single Read Accesses Functional OverviewAddress Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics CE2 Adsp Adsc ADV Write CLKFunction CY7C1380C Truth Table for Read/Write5CLK Adsp Adsc ADV Write BWETAP Controller Block Diagram TAP Controller State Diagram Ieee 1149.1 Serial Boundary Scan JtagIdentification ID Register Bypass RegisterBoundary Scan Register TAP Instruction SetTAP AC Switching Characteristics Over the operating Range9 TAP Timing5V TAP AC Output Load Equivalent 3V TAP AC Test ConditionsParameter Description Test Conditions MIN MAX Units Scan Register Sizes Identification Register DefinitionsIdentification Codes Ball BGA Boundary Scan Order CY7C1380C 512K x Ball BGA Boundary Scan Order CY7C1382C 1M x F10 G10 Ball fBGA Boundary Scan Order CY7C1380C 512K xA10 J10Ball fBGA Boundary Scan Order CY7C1382C 1M x Operating Range Electrical Characteristics Over the Operating Range12Maximum Ratings Ambient RangeParameter Description Test Conditions Thermal Resistance14Capacitance FBGA Unit3V I/O Test Load AC Test Loads and Waveforms5V I/O Test Load Switching Characteristics Over the Operating Range19 Min Max UnitSwitching Waveforms Read Cycle Timing21Write Cycle Timing21 Read/Write Cycle Timing21, 23 CLZZZ Mode Timing 25 CY7C1382C-250AC CY7C1380C-250BGC Ordering InformationCY7C1382C-167AI CY7C1380C-167BGI Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A101Lead Pbga 14 x 22 x 2.4 mm BG119 Package Diagrams Document History Issue Date Orig. Description of ChangeREV ECN no