Read/Write Cycle Timing21, 23, Clz | Cypress CY7C1382C, CY7C1380C

CY7C1380C

CY7C1382C

Switching Waveforms (continued)

Read/Write Cycle Timing[21, 23, 24]

			tCYC
CLK
		tCH	tCL
	tADS	tADH
ADSP
ADSC
	tAS	tAH
ADDRESS	A1	A2
BWE,
BWX
	tCES	tCEH
CE
ADV
OE
			tCO

A3 A4

tWES tWEH

tDS tDH

A5 A6

Data In (D)	High-Z	t	tOEHZ
		t	tOEHZ
		CLZ
Data Out (Q)	High-Z	Q(A1)	Q(A2)

D(A3)

tOELZ

Q(A4) Q(A4+1) Q(A4+2) Q(A4+3)

D(A5) D(A6)

Back-to-Back READs

Single WRITE	BURST READ
DON’T CARE	UNDEFINED

Back-to-Back

WRITEs

Note:

23.The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.

24.GW is HIGH.

Document #: 38-05237 Rev. *D

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Cypress CY7C1382C, CY7C1380C manual Read/Write Cycle Timing21, 23, Clz

Contents

Selection Guide FeaturesFunctional Description1 250 MHz 225 MHz 200 MHz 167 MHz 133 MHz Unit Logic Block Diagram CY7C1380C 512K x Logic Block Diagram CY7C1382C 1M x Pin Configurations CY7C1380C 512K XCY7C1382C 1M x NC / 72M NC / 36M CY7C1382C 512K x NC / 288M NC / 72M CY7C1380C-Pin Definitions Tqfp BGA On the rising edge of CLK, active LOW. When Power supply inputs to the core of the deAddress Strobe from Processor, sampled Address Strobe from Controller, sampled on Ground for the I/O circuitry Power supply for the I/O circuitrySelects Burst Order . When tied to GND Serial data-out to the Jtag circuit . Delivers CY7C1382CPin Definitions Power supply inputs to the core of the device Rising edge of CLK, active LOW . When assertedZZ sleep Input, active High . When asserted Address Strobe from Processor, sampled on Serial data-out to the Jtag circuit . Delivers data Single Read Accesses Functional Overview Address Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics CE2 Adsp Adsc ADV Write CLK Function CY7C1380C Truth Table for Read/Write5CLK Adsp Adsc ADV Write BWE TAP Controller Block Diagram TAP Controller State Diagram Ieee 1149.1 Serial Boundary Scan Jtag Identification ID Register Bypass RegisterBoundary Scan Register TAP Instruction Set TAP AC Switching Characteristics Over the operating Range9 TAP Timing 3V TAP AC Test Conditions 5V TAP AC Output Load EquivalentParameter Description Test Conditions MIN MAX Units Identification Register Definitions Scan Register SizesIdentification Codes Ball BGA Boundary Scan Order CY7C1380C 512K x Ball BGA Boundary Scan Order CY7C1382C 1M x F10 G10 Ball fBGA Boundary Scan Order CY7C1380C 512K xA10 J10 Ball fBGA Boundary Scan Order CY7C1382C 1M x Operating Range Electrical Characteristics Over the Operating Range12Maximum Ratings Ambient Range Parameter Description Test Conditions Thermal Resistance14Capacitance FBGA Unit AC Test Loads and Waveforms 3V I/O Test Load5V I/O Test Load Switching Characteristics Over the Operating Range19 Min Max Unit Switching Waveforms Read Cycle Timing21 Write Cycle Timing21 Read/Write Cycle Timing21, 23 CLZ ZZ Mode Timing 25 Ordering Information CY7C1382C-250AC CY7C1380C-250BGCCY7C1382C-167AI CY7C1380C-167BGI Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A101 Lead Pbga 14 x 22 x 2.4 mm BG119 Package Diagrams Issue Date Orig. Description of Change Document HistoryREV ECN no