Cypress CY7C1380C, CY7C1382C Switching Characteristics Over the Operating Range19, Min Max Unit

CY7C1380C

CY7C1382C

Switching Characteristics Over the Operating Range[19, 20]

																		250 MHz		225 MHz		200 MHz		167 MHz		133 MHz
Parameter														Description				Min.	Max					Min.	Max	Min.	Max	Unit
tPOWER	VDD(Typical) to the first Access[15]																	1		1		1		1		1		ms
Clock
tCYC	Clock Cycle Time																	4.0		4.4		5		6		7.5		ns
tCH	Clock HIGH																	1.7		2.0		2.0		2.2		2.5		ns
tCL	Clock LOW																	1.7		2.0		2.0		2.2		2.5		ns
Output Times
tCO	Data Output Valid After CLK Rise																		2.6		2.8		3.0		3.4		4.2	ns
tDOH	Data Output Hold After CLK Rise																	1.0		1.0		1.3		1.3		1.3		ns
tCLZ	Clock to Low-Z[16,17, 18]																	1.0		1.0		1.3		1.3		1.3		ns
tCHZ	Clock to High-Z[16,17, 18]																		2.6		2.8		3.0		3.4		3.4	ns
tOEV		LOW to Output Valid																	2.6		2.8		3.0		3.4		4.2	ns
	OE
tOELZ		LOW to Output Low-Z[16, 17, 18]																0		0		0		0		0		ns
	OE
tOEHZ		HIGH to Output High-Z[16, 17, 18]																	2.6		2.8		3.0		3.4		4.0	ns
	OE
Setup Times
tAS	Address Set-up Before CLK Rise																	1.2		1.4		1.4		1.5		1.5		ns
tADS								,							Set-up Before CLK			1.2		1.4		1.4		1.5		1.5		ns
	ADSC								ADSP
	Rise
tADVS						Set-up Before CLK Rise												1.2		1.4		1.4		1.5		1.5		ns
	ADV
tWES																	Set-up Before CLK	1.2		1.4		1.4		1.5		1.5		ns
	GW,					BWE,							BW
	Rise																X
tDS	Data Input Set-up Before CLK Rise																	1.2		1.4		1.4		1.5		1.5		ns
tCES	Chip Enable Set-Up Before CLK Rise																	1.2		1.4		1.4		1.5		1.5		ns
Hold Times
tAH	Address Hold After CLK Rise																	0.3		0.4		0.4		0.5		0.5		ns
tADH							,									Hold After CLK Rise		0.3		0.4		0.4		0.5		0.5		ns
	ADSP									ADSC
tADVH					Hold After CLK Rise													0.3		0.4		0.4		0.5		0.5		ns
	ADV
tWEH			,								,					X Hold After CLK Rise		0.3		0.4		0.4		0.5		0.5		ns
	GW			BWE								BW
tDH	Data Input Hold After CLK Rise																	0.3		0.4		0.4		0.5		0.5		ns
tCEH	Chip Enable Hold After CLK Rise																	0.3		0.4		0.4		0.5		0.5		ns

Shaded areas contain advance information.

Notes:

15.This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD( minimum) initially before a read or write operation can be initiated.

16.tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.

17.At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions

18.This parameter is sampled and not 100% tested.

19.Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V.

20.Test conditions shown in (a) of AC Test Loads unless otherwise noted.

Document #: 38-05237 Rev. *D Page 27 of 36

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