NC / 72M NC / 36M, CY7C1382C 512K x | Cypress CY7C1380C guide

CY7C1380C

CY7C1382C

Pin Configurations (continued)

119-ball BGA (1 Chip Enable with JTAG)

CY7C1380C (512K x 36)

1

2

3

4

5

6

7

A

VDDQ

A

A

A

A

VDDQ

ADSP

B

NC

A

A

A

A

NC

ADSC

C

NC

A

A

VDD

A

A

NC

D

DQC

DQPC

VSS

NC

VSS

DQPB

DQB

E

DQC

DQC

VSS

1

VSS

DQB

DQB

CE

F

VDDQ

DQC

VSS

VSS

DQB

VDDQ

OE

G

DQC

DQC

C

B

DQB

DQB

BW

ADV

BW

H

DQC

DQC

VSS

VSS

DQB

DQB

GW

J

VDDQ

VDD

NC

VDD

NC

VDD

VDDQ

K

DQD

DQD

VSS

CLK

VSS

DQA

DQA

L

DQD

DQD

D

NC

A

DQA

DQA

BW

BW

M

VDDQ

DQD

VSS

VSS

DQA

VDDQ

BWE

N

DQD

DQD

VSS

A1

VSS

DQA

DQA

P

DQD

DQPD

VSS

A0

VSS

DQPA

DQA

R

NC

A

MODE

VDD

NC

A

NC

T

NC

NC / 72M

A

A

A

NC / 36M

ZZ

U

VDDQ

TMS

TDI

TCK

TDO

NC

VDDQ

CY7C1382C (512K x 18)

1

2

3

4

5

6

7

A

VDDQ

A

A

A

A

VDDQ

ADSP

B

NC

A

A

A

A

NC

ADSC

C

NC

A

A

VDD

A

A

NC

D

DQB

NC

VSS

NC

VSS

DQPA

NC

E

NC

DQB

VSS

1

VSS

NC

DQA

CE

F

VDDQ

NC

VSS

VSS

DQA

VDDQ

OE

G

NC

DQB

B

VSS

NC

DQA

BW

ADV

H

DQB

NC

VSS

VSS

DQA

NC

GW

J

VDDQ

VDD

NC

VDD

NC

VDD

VDDQ

K

NC

DQB

VSS

CLK

VSS

NC

DQA

L

DQB

NC

VSS

NC

A

DQA

NC

BW

M

VDDQ

DQB

VSS

VSS

NC

VDDQ

BWE

N

DQB

NC

VSS

A1

VSS

DQA

NC

P

NC

DQPB

VSS

A0

VSS

NC

DQA

R

NC

A

MODE

VDD

NC

A

NC

T

NC / 72M

A

A

NC / 36M

A

A

ZZ

U

VDDQ

TMS

TDI

TCK

TDO

NC

VDDQ

Document #: 38-05237 Rev. *D

Page 4 of 36

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Cypress CY7C1380C manual NC / 72M NC / 36M, CY7C1382C 512K x

Contents

Features Functional Description1Selection Guide 250 MHz 225 MHz 200 MHz 167 MHz 133 MHz Unit Logic Block Diagram CY7C1380C 512K x Logic Block Diagram CY7C1382C 1M x CY7C1380C 512K X Pin ConfigurationsCY7C1382C 1M x NC / 72M NC / 36M CY7C1382C 512K x NC / 288M NC / 72M CY7C1380C-Pin Definitions Tqfp BGA Power supply inputs to the core of the de Address Strobe from Processor, sampledOn the rising edge of CLK, active LOW. When Address Strobe from Controller, sampled on Power supply for the I/O circuitry Selects Burst Order . When tied to GNDGround for the I/O circuitry Serial data-out to the Jtag circuit . Delivers CY7C1382CPin Definitions Rising edge of CLK, active LOW . When asserted ZZ sleep Input, active High . When assertedPower supply inputs to the core of the device Address Strobe from Processor, sampled on Serial data-out to the Jtag circuit . Delivers data Single Read Accesses Functional Overview Interleaved Burst Address Table Mode = Floating or VDD ZZ Mode Electrical CharacteristicsAddress CE2 Adsp Adsc ADV Write CLK Truth Table for Read/Write5 CLK Adsp Adsc ADV WriteFunction CY7C1380C BWE TAP Controller Block Diagram TAP Controller State Diagram Ieee 1149.1 Serial Boundary Scan Jtag Bypass Register Boundary Scan RegisterIdentification ID Register TAP Instruction Set TAP AC Switching Characteristics Over the operating Range9 TAP Timing 5V TAP AC Output Load Equivalent 3V TAP AC Test ConditionsParameter Description Test Conditions MIN MAX Units Scan Register Sizes Identification Register DefinitionsIdentification Codes Ball BGA Boundary Scan Order CY7C1380C 512K x Ball BGA Boundary Scan Order CY7C1382C 1M x Ball fBGA Boundary Scan Order CY7C1380C 512K x A10F10 G10 J10 Ball fBGA Boundary Scan Order CY7C1382C 1M x Electrical Characteristics Over the Operating Range12 Maximum RatingsOperating Range Ambient Range Thermal Resistance14 CapacitanceParameter Description Test Conditions FBGA Unit 3V I/O Test Load AC Test Loads and Waveforms5V I/O Test Load Switching Characteristics Over the Operating Range19 Min Max Unit Switching Waveforms Read Cycle Timing21 Write Cycle Timing21 Read/Write Cycle Timing21, 23 CLZ ZZ Mode Timing 25 CY7C1382C-250AC CY7C1380C-250BGC Ordering InformationCY7C1382C-167AI CY7C1380C-167BGI Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A101 Lead Pbga 14 x 22 x 2.4 mm BG119 Package Diagrams Document History Issue Date Orig. Description of ChangeREV ECN no