Cypress CY7C68053 ECC1B2, COL5 COL4 COL3 COL2 COL1 COL0 LINE17 LINE16, ECC2B0, ECC2B1, ECC2B2

Models: CY7C68053

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CY7C68053

Table 5-1. FX2LP18 Register Summary (continued)

Hex

Size

Name

Description

b7

b6

b5

b4

b3

b2

b1

b0

Default

Access

E62C

1

ECC1B2

ECC1 Byte 2 Address

COL5

COL4

COL3

COL2

COL1

COL0

LINE17

LINE16

00000000

R

E62D

1

ECC2B0

ECC2 Byte 0 Address

LINE15

LINE14

LINE13

LINE12

LINE11

LINE10

LINE9

LINE8

00000000

R

E62E

1

ECC2B1

ECC2 Byte 1 Address

LINE7

LINE6

LINE5

LINE4

LINE3

LINE2

LINE1

LINE0

00000000

R

E62F

1

ECC2B2

ECC2 Byte 2 Address

COL5

COL4

COL3

COL2

COL1

COL0

0

0

00000000

R

E630

1

EP2FIFOPFH[10]

Endpoint 2/slave FIFO

DECIS

PKTSTAT

IN:PKTS[2]

IN:PKTS[1]

IN:PKTS[0]

0

PFC9

PFC8

10001000

bbbbbrbb

H.S.

 

 

Programmable Flag H

 

 

OUT:PFC12

OUT:PFC11

OUT:PFC10

 

 

 

 

 

E630

1

EP2FIFOPFH[10]

Endpoint 2/slave FIFO

DECIS

PKTSTAT

OUT:PFC12

OUT:PFC11

OUT:PFC10

0

PFC9

IN:PKTS[2]

10001000

bbbbbrbb

F.S.

 

 

Programmable Flag H

 

 

 

 

 

 

 

OUT:PFC8

 

 

E631

1

EP2FIFOPFL[10]

Endpoint 2/slave FIFO

PFC7

PFC6

PFC5

PFC4

PFC3

PFC2

PFC1

PFC0

00000000

RW

H.S.

 

 

Programmable Flag L

 

 

 

 

 

 

 

 

 

 

E631

1

EP2FIFOPFL[10]

Endpoint 2/slave FIFO

IN:PKTS[1]

IN:PKTS[0]

PFC5

PFC4

PFC3

PFC2

PFC1

PFC0

00000000

RW

F.S

 

 

Programmable Flag L

OUT:PFC7

OUT:PFC6

 

 

 

 

 

 

 

 

E632

1

EP4FIFOPFH[10]

Endpoint 4/slave FIFO

DECIS

PKTSTAT

0

IN: PKTS[1]

IN: PKTS[0]

0

0

PFC8

10001000

bbrbbrrb

H.S.

 

 

Programmable Flag H

 

 

 

OUT:PFC10

OUT:PFC9

 

 

 

 

 

E632

1

EP4FIFOPFH[10]

Endpoint 4/slave FIFO

DECIS

PKTSTAT

0

OUT:PFC10

OUT:PFC9

0

0

PFC8

10001000

bbrbbrrb

F.S

 

 

Programmable Flag H

 

 

 

 

 

 

 

 

 

 

E633

1

EP4FIFOPFL[10]

Endpoint 4/slave FIFO

PFC7

PFC6

PFC5

PFC4

PFC3

PFC2

PFC1

PFC0

00000000

RW

H.S.

 

 

Programmable Flag L

 

 

 

 

 

 

 

 

 

 

E633

1

EP4FIFOPFL[10]

Endpoint 4/slave FIFO

IN: PKTS[1]

IN: PKTS[0]

PFC5

PFC4

PFC3

PFC2

PFC1

PFC0

00000000

RW

F.S

 

 

Programmable Flag L

OUT:PFC7

OUT:PFC6

 

 

 

 

 

 

 

 

E634

1

EP6FIFOPFH[10]

Endpoint 6/slave FIFO

DECIS

PKTSTAT

IN:PKTS[2]

IN:PKTS[1]

IN:PKTS[0]

0

PFC9

PFC8

00001000

bbbbbrbb

H.S.

 

 

Programmable Flag H

 

 

OUT:PFC12

OUT:PFC11

OUT:PFC10

 

 

 

 

 

E634

1

EP6FIFOPFH[10]

Endpoint 6/slave FIFO

DECIS

PKTSTAT

OUT:PFC12

OUT:PFC11

OUT:PFC10

0

PFC9

IN:PKTS[2]

00001000

bbbbbrbb

F.S

 

 

Programmable Flag H

 

 

 

 

 

 

 

OUT:PFC8

 

 

E635

1

EP6FIFOPFL[10]

Endpoint 6/slave FIFO

PFC7

PFC6

PFC5

PFC4

PFC3

PFC2

PFC1

PFC0

00000000

RW

H.S.

 

 

Programmable Flag L

 

 

 

 

 

 

 

 

 

 

E635

1

EP6FIFOPFL[10]

Endpoint 6/slave FIFO

IN:PKTS[1]

IN:PKTS[0]

PFC5

PFC4

PFC3

PFC2

PFC1

PFC0

00000000

RW

F.S

 

 

Programmable Flag L

OUT:PFC7

OUT:PFC6

 

 

 

 

 

 

 

 

E636

1

EP8FIFOPFH[10]

Endpoint 8/slave FIFO

DECIS

PKTSTAT

0

IN: PKTS[1]

IN: PKTS[0]

0

0

PFC8

00001000

bbrbbrrb

H.S.

 

 

Programmable Flag H

 

 

 

OUT:PFC10

OUT:PFC9

 

 

 

 

 

E636

1

EP8FIFOPFH[10]

Endpoint 8/slave FIFO

DECIS

PKTSTAT

0

OUT:PFC10

OUT:PFC9

0

0

PFC8

00001000

bbrbbrrb

F.S

 

 

Programmable Flag H

 

 

 

 

 

 

 

 

 

 

E637

1

EP8FIFOPFL[10]

Endpoint 8/slave FIFO

PFC7

PFC6

PFC5

PFC4

PFC3

PFC2

PFC1

PFC0

00000000

RW

H.S.

 

 

Programmable Flag L

 

 

 

 

 

 

 

 

 

 

E637

1

EP8FIFOPFL[10]

Endpoint 8/slave FIFO

IN: PKTS[1]

IN: PKTS[0]

PFC5

PFC4

PFC3

PFC2

PFC1

PFC0

00000000

RW

F.S

 

 

Programmable Flag L

OUT:PFC7

OUT:PFC6

 

 

 

 

 

 

 

 

 

8

Reserved

 

 

 

 

 

 

 

 

 

 

 

E640

1

EP2ISOINPKTS

EP2 (if ISO) IN Packets

AADJ

0

0

0

0

0

INPPF1

INPPF0

00000001

brrrrrbb

 

 

 

per frame (1-3)

 

 

 

 

 

 

 

 

 

 

E641

1

EP4ISOINPKTS

EP4 (if ISO) IN Packets

AADJ

0

0

0

0

0

INPPF1

INPPF0

00000001

brrrrrrr

 

 

 

per frame (1-3)

 

 

 

 

 

 

 

 

 

 

E642

1

EP6ISOINPKTS

EP6 (if ISO) IN Packets

AADJ

0

0

0

0

0

INPPF1

INPPF0

00000001

brrrrrbb

 

 

 

per frame (1-3)

 

 

 

 

 

 

 

 

 

 

E643

1

EP8ISOINPKTS

EP8 (if ISO) IN Packets

AADJ

0

0

0

0

0

INPPF1

INPPF0

00000001

brrrrrrr

 

 

 

per frame (1-3)

 

 

 

 

 

 

 

 

 

 

E644

4

Reserved

 

 

 

 

 

 

 

 

 

 

 

E648

1

INPKTEND[10]

Force IN Packet End

Skip

0

0

0

EP3

EP2

EP1

EP0

xxxxxxxx

W

E649

7

OUTPKTEND[10]

Force OUT Packet End

Skip

0

0

0

EP3

EP2

EP1

EP0

xxxxxxxx

W

 

 

INTERRUPTS

 

 

 

 

 

 

 

 

 

 

 

E650

1

EP2FIFOIE[10]

Endpoint 2 slave FIFO

0

0

0

0

EDGEPF

PF

EF

FF

00000000

RW

 

 

 

Flag Interrupt Enable

 

 

 

 

 

 

 

 

 

 

E651

1

EP2FIFOIRQ[10,11]

Endpoint 2 slave FIFO

0

0

0

0

0

PF

EF

FF

00000000

rrrrrbbb

 

 

 

Flag Interrupt Request

 

 

 

 

 

 

 

 

 

 

E652

1

EP4FIFOIE[10]

Endpoint 4 slave FIFO

0

0

0

0

EDGEPF

PF

EF

FF

00000000

RW

 

 

 

Flag Interrupt Enable

 

 

 

 

 

 

 

 

 

 

E653

1

EP4FIFOIRQ[10,11]

Endpoint 4 slave FIFO

0

0

0

0

0

PF

EF

FF

00000000

rrrrrbbb

 

 

 

Flag Interrupt Request

 

 

 

 

 

 

 

 

 

 

E654

1

EP6FIFOIE[10]

Endpoint 6 slave FIFO

0

0

0

0

EDGEPF

PF

EF

FF

00000000

RW

 

 

 

Flag Interrupt Enable

 

 

 

 

 

 

 

 

 

 

E655

1

EP6FIFOIRQ[10,11]

Endpoint 6 slave FIFO

0

0

0

0

0

PF

EF

FF

00000000

rrrrrbbb

 

 

 

Flag Interrupt Request

 

 

 

 

 

 

 

 

 

 

E656

1

EP8FIFOIE[10]

Endpoint 8 slave FIFO

0

0

0

0

EDGEPF

PF

EF

FF

00000000

RW

 

 

 

Flag Interrupt Enable

 

 

 

 

 

 

 

 

 

 

E657

1

EP8FIFOIRQ[10,11]

Endpoint 8 slave FIFO

0

0

0

0

0

PF

EF

FF

00000000

rrrrrbbb

 

 

 

Flag Interrupt Request

 

 

 

 

 

 

 

 

 

 

E658

1

IBNIE

IN-BULK-NAK Interrupt

0

0

EP8

EP6

EP4

EP2

EP1

EP0

00000000

RW

 

 

 

Enable

 

 

 

 

 

 

 

 

 

 

E659

1

IBNIRQ[11]

IN-BULK-NAK interrupt

0

0

EP8

EP6

EP4

EP2

EP1

EP0

00xxxxxx

rrbbbbbb

 

 

 

Request

 

 

 

 

 

 

 

 

 

 

E65A

1

NAKIE

Endpoint Ping-NAK/IBN

EP8

EP6

EP4

EP2

EP1

EP0

0

IBN

00000000

RW

 

 

 

Interrupt Enable

 

 

 

 

 

 

 

 

 

 

E65B

1

NAKIRQ[11]

Endpoint Ping-NAK/IBN

EP8

EP6

EP4

EP2

EP1

EP0

0

IBN

xxxxxx0x

bbbbbbrb

 

 

 

Interrupt Request

 

 

 

 

 

 

 

 

 

 

E65C

1

USBIE

USB Int Enables

0

EP0ACK

HSGRANT

URES

SUSP

SUTOK

SOF

SUDAV

00000000

RW

E65D

1

USBIRQ[11]

USB Interrupt Requests

0

EP0ACK

HSGRANT

URES

SUSP

SUTOK

SOF

SUDAV

0xxxxxxx

rbbbbbbb

Note

11. The register can only be reset, it cannot be set.

Document # 001-06120 Rev *F

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Cypress CY7C68053 ECC1B2, COL5 COL4 COL3 COL2 COL1 COL0 LINE17 LINE16, ECC2B0, ECC2B1, ECC2B2, EP2FIFOPFH, EP2FIFOPFL

CY7C68053 specifications

The Cypress CY7C68053 is a versatile USB microcontroller known for its strong performance and rich feature set, catering to a wide range of applications requiring USB connectivity. Part of the Cypress family of USB products, this microcontroller combines the convenience of USB interfacing with powerful embedded processing capabilities.

At its core, the CY7C68053 is built on an 8051 microcontroller architecture, enabling efficient data handling and control operations. It operates at speeds of up to 48 MHz, providing ample processing power for complex applications. The device features an integrated USB 2.0 full-speed controller, which allows for high-speed data transfer rates of up to 12 Mbps. This makes it ideal for applications such as data transfer, communication devices, and real-time processing tasks.

One of the standout features of the CY7C68053 is its flexible pin configuration. It supports a variety of operating modes, including peripheral mode, host mode, and a combination of both, allowing it to cater to diverse application requirements. Additionally, the device offers a large number of GPIO pins that can be used for various control and communication tasks. This flexibility ensures that developers can tailor the hardware to meet the specific needs of their application.

In terms of development, the CY7C68053 is backed by a robust set of software development tools from Cypress. The EZ-USB development kit provides a comprehensive platform for firmware development, testing, and debugging. This kit includes libraries, example projects, and a user-friendly integrated development environment (IDE), streamlining the development process for engineers.

The CY7C68053 is also equipped with an extensive memory system, featuring 32 kB of in-system programmable Flash memory, 2 kB of SRAM, and 128 bytes of EEPROM. This memory capacity allows for the storage of complex firmware and user data, enhancing the device's versatility.

Moreover, the CY7C68053 is designed with low power consumption in mind. It includes power management features that allow it to operate efficiently, making it suitable for battery-operated devices.

In summary, the Cypress CY7C68053 stands out as a powerful USB microcontroller that combines high-speed processing, flexible configurations, and robust software support. Its features make it an excellent choice for developers looking to create innovative USB-enabled products across various applications.