Cypress CY7C68053 10.0 Ordering Information, 11.0 Package Diagram

CY7C68053

Document # 001-06120 Rev *F Page 37 of 39

10.0 Ordering Information11.0 Package Diagram

The FX2LP18 is available in a 56-pin VFBGA package.

Figure 11-1. 56 VFBGA (5 x 5 x 1.0 mm) 0.50 Pitch, 0.30 Ball BZ56

Table 10-1. Ordering Information

Ordering Code Package Type RAM Size # Prog I/Os

8051

Address/Data

Busses

CY7C68053-56BAXI 56 VFBGA– Lead-Free 16K 24 –

Development Tool Kit

CY3687 MoBL-USB FX2LP18 Development Kit

TOPVIEW

PINA1 CORNER

0.50

3.50

5.00±0.10

BOTTOMVIEW

0.10(4X)

3.50

5.00±0.10

0.50

Ø0.15MC A B

Ø0.05MC

Ø0.30±0.05(56X)

A1CORNER

-B-

-A-

1.0max

0.160~0.260

0.080C

0.45

SEATINGPLANE

0.21

0.10C

-C-

SIDEVIEW

5.00±0.10

REFERENCEJEDEC: MO-195C

PACKAGEWEIGHT: 0.02 grams

132654867856 2341

001-03901-*B

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Contents

Main MoBL-USB FX2LP18 USB Microcontroller 1.0 CY7C68053 Features MoBL-USB FX2LP18 Block Diagram 2.0 Applications 3.0 Functional Overview 3.1 USB Signaling Speed 3.2 8051 Microprocessor CY7C68053 3.3 I2C Bus 3.4 Buses 3.5 USB Boot Methods 3.6 ReNumeration Page CY7C68053 3.9 Reset and Wakeup CY7C68053 3.10 Program/Data RAM 3.11 Register Addresses 3.12 Endpoint RAM Page CY7C68053 3.13 External FIFO Interface 3.14 GPIF 3.15 ECC Generation 3.16 USB Uploads and Downloads 3.17 Autopointer Access 3.18 I2C Controller 4.0 Pin Assignments Port GPIF Master Slave FIFO Figure 4-2. CY7C68053 56-pin VFBGA Pin Assignment - Top view 4.1 CY7C68053 Pin Descriptions Appropriate bulk/bypass capacitance should be provided for this Page Page Page 5.0 Register Summary Note 11. The register can only be reset, it cannot be set. Table 5-1. FX2LP18 Register Summary (continued) Page Document # 001-06120 Rev *F Page 20 of 39 Page Page 6.0 Absolute Maximum Ratings 7.0 Operating Conditions 8.0 DC Characteristics 9.0 AC Electrical Characteristics 9.1 USB Transceiver 9.2 GPIF Synchronous Signals 9.3 Slave FIFO Synchronous Read 9.4 Slave FIFO Asynchronous Read 9.5 Slave FIFO Synchronous Write 9.6 Slave FIFO Asynchronous Write 9.7 Slave FIFO Synchronous Packet End Strobe 9.8 Slave FIFO Asynchronous Packet End Strobe 9.9 Slave FIFO Output Enable 9.10 Slave FIFO Address to Flags/Data 9.11 Slave FIFO Synchronous Address 9.12 Slave FIFO Asynchronous Address 9.13 Sequence Diagram Page Page Page 10.0 Ordering Information 11.0 Package Diagram Table 10-1. Ordering Information Ordering Code Package Type RAM Size # Prog I/Os 12.0 PCB Layout Recommendations Document History Page