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Cypress CY7C68053 manual Ordering Information, Package Diagram, Development Tool Kit

Models: CY7C68053

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CY7C68053

10.0Ordering Information

Table 10-1. Ordering Information

				8051
Ordering Code	Package Type	RAM Size	# Prog I/Os	Address/Data
Ordering Code	Package Type	RAM Size	# Prog I/Os	Busses
CY7C68053-56BAXI	56 VFBGA– Lead-Free	16K	24	–


Development Tool Kit
CY3687	MoBL-USB FX2LP18 Development Kit

11.0Package Diagram

The FX2LP18 is available in a 56-pin VFBGA package.

Figure 11-1. 56 VFBGA (5 x 5 x 1.0 mm) 0.50 Pitch, 0.30 Ball BZ56

TOP VIEW

PIN A1 CORNER

1 2 3 4 5 6 6 8

			A
			B
	5.00±0.10		C
	5.00±0.10		D
			D
			E
			F
			G
			H

	5.00±0.10
	SIDE VIEW	C
	SIDE VIEW	0.10
0.45		0.10	0.080 C
-C-	SEATING PLANE
0.21		~0.260	1.0 max
		0.160

BOTTOM VIEW

			Ø0.05 M C
				Ø0.15 M C A B					A1 CORNER
			Ø0.30±0.05(56X)
		8	7	6	5	4	3	2	1
									A
5.00±0.10	3.50	0.50							B
5.00±0.10	3.50	0.50							C
									C
									D
									E
									F
									G

H

0.50

-B-

3.50

-A-

5.00±0.10

0.10(4X)

REFERENCE JEDEC: MO-195C

PACKAGE WEIGHT: 0.02 grams

001-03901-*B

Document # 001-06120 Rev *F

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Cypress CY7C68053 manual Ordering Information, Package Diagram, Development Tool Kit

Contents

Block Diagram CY7C68053 FeaturesCypress Semiconductor Corporation Applications USB Signaling SpeedFunctional Overview 8051 MicroprocessorBus-powered Applications USB Boot MethodsI2C Bus BusesPriority INT2VEC Value Source INT2 USB InterruptsReset Timing Values Reset and WakeupCondition Register Addresses Program/Data RAMEndpoint RAM Default Full-Speed Alternate Settings3 Default Full-Speed Alternate SettingsExternal Fifo Interface Default High-Speed Alternate Settings3Gpif USB Uploads and Downloads Autopointer AccessECC Generation6 18 I2C Controller18.3 I2C Interface General Purpose Access 18.2 I2C Interface Boot Load AccessPin Assignments CY7C68053 56-pin Vfbga Pin Assignment Top view CY7C68053 Pin Descriptions Name Type Default DescriptionFX2LP18 Pin Descriptions Port aFIFOADR1 FIFOADR0Pktend SLCS#Slwr IFCONFIG10 Slrd IFCONFIG10Flaga IFCONFIG10 Flagb IFCONFIG10Ground FX2LP18 Register Summary Register SummaryCOL5 COL4 COL3 COL2 COL1 COL0 LINE17 LINE16 ECC1B2ECC2B0 ECC2B1Epie Qenable Qstate QSIGNAL2 QSIGNAL1 QSIGNAL0EP8 EP6 EP4 EP2 EP1OUT EP1IN EP0OUT EP0IN Gpifwf GpifdoneBusy Stall EP1OUTCSEP1INCS EP2CSTC9 TC8 E6CFTC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0 EP2GPIFFLGSELDPL0 AutoptrsetupDPH0 SELRCAP2H RCAP2LTL2 TH2Operating Conditions Absolute Maximum RatingsDC Characteristics Gpif Synchronous Signals AC Electrical CharacteristicsUSB Transceiver Slave Fifo Synchronous Read Slave Fifo Synchronous Read Timing Diagram17Slave Fifo Asynchronous Read Slave Fifo Asynchronous Read Timing Diagram17Slave Fifo Synchronous Write Slave Fifo Synchronous Write Timing Diagram17Slave Fifo Synchronous Packet End Strobe Slave Fifo Asynchronous WriteSlave Fifo Asynchronous Packet End Strobe Slave Fifo Synchronous Write Sequence and Timing DiagramSlave Fifo Address to Flags/Data Slave Fifo Output EnableSlave Fifo Asynchronous Address Slave Fifo Synchronous AddressSingle and Burst Synchronous Read Example Sequence DiagramIfclk Sloe SlrdSingle and Burst Synchronous Write 17. Slave Fifo Asynchronous Read Sequence of Events Diagram Sequence Diagram of a Single and Burst Asynchronous ReadSequence Diagram of a Single and Burst Asynchronous Write Ordering Information Package DiagramDevelopment Tool Kit PCB Layout Recommendations Document History Issue Date Orig. Description of ChangeOSG ARI