Cypress CY7C68053 manual Reset and Wakeup, Reset Timing Values, Condition

CY7C68053

Figure 3-2. Reset Timing Plots

RESET#	RESET#
	VIL
	1.8V
	1.62V
VCC	VCC
	0V
	TRESET

Power on Reset

VIL

1.8V

0V

TRESET

Powered Reset

3.9Reset and Wakeup

The reset and wakeup pins are described in detail in this section.

3.9.1Reset Pin

The input pin, RESET#, resets the FX2LP18 when asserted. This pin has hysteresis and is active LOW. When a crystal is used with the CY7C68053, the reset period must allow for the stabilization of the crystal and the PLL. This reset period must be approximately 5 ms after VCC has reached 3.0V. If the crystal input pin is driven by a clock signal the internal PLL stabilizes in 200 ∝s after VCC has reached 3.0V[2]. Figure 3-2shows a power on reset condition and a reset applied during operation. A power on reset is defined as the time reset is asserted while power is being applied to the circuit. A powered reset is defined to be when the FX2LP18 has previously been powered on and operating and the RESET# pin is asserted.

Cypress provides an application note which describes and recommends power on reset implementation and can be found on the Cypress web site. For more information on reset imple- mentation for the MoBL-USB™ family of products, visit the Cypress web site at http://www.cypress.com.

The FX2LP18 exits the power-down (USB suspend) state using one of the following methods:

•USB bus activity (if D+/D– lines are left floating, noise on these lines may indicate activity to the FX2LP18 and initiate a wakeup)

•External logic asserts the WAKEUP pin

•External logic asserts the PA3/WU2 pin

The second wakeup pin, WU2, can also be configured as a general purpose IO pin. This allows a simple external R-C network to be used as a periodic wakeup source. Note that WAKEUP is by default active LOW.

3.9.3Lowering Suspend Current

Good design practices for CMOS circuits dictate that any unused input pins must not be floating between VIL and VIH. Floating input pins will not damage the chip, but can substan- tially increase suspend current. To achieve the lowest suspend current, any unused port pins must be configured as outputs. Any unused input pins must be tied to ground. Some examples of pins that need attention during suspend are:

•Port pins. For Port A, B, D pins, extra care must be taken in shared bus situations.

Table 3-3. Reset Timing Values	— Completely unused pins must be pulled to VCC_IO or
	GND.

Condition	TRESET
Power on Reset with crystal	5 ms
Power on Reset with external	200 ∝s + Clock stability time
clock
Powered Reset	200 ∝s

3.9.2Wakeup Pins

The 8051 puts itself and the rest of the chip into a power-down mode by setting PCON.0 = 1. This stops the oscillator and PLL. When WAKEUP is asserted by external logic, the oscillator restarts, after the PLL stabilizes, and then the 8051 receives a wakeup interrupt. This applies whether or not FX2LP18 is connected to the USB.

Note

—In a single-master system, the firmware must output en- able all the port pins and drive them high or low, before FX2LP18 enters the suspend state.

—In a multi-master system (FX2LP18 and another proces- sor sharing a common data bus), when FX2LP18 is sus- pended, the external master must drive the pins high or low. The external master may not let the pins float.

•CLKOUT. If CLKOUT is not used, it must be tri-stated during normal operation, but driven during suspend.

•IFCLK, RDY0, RDY1. These pins must be pulled to VCC_IO or GND or driven by another chip.

•CTL0-2. If tri-stated via GPIFIDLECTL, these pins must be pulled to VCC_IO or GND or driven by another chip.

•RESET#, WAKEUP#. These pins must be pulled to VCC_IO or GND or driven by another chip during suspend.

2.If the external clock is powered at the same time as the CY7C680xx and has a stabilization wait period, it must be added to the 200 ∝s.

Document # 001-06120 Rev *F Page 5 of 39

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