Cypress CY7C68053 - page 22

CY7C68053

Document # 001-06120 Rev *F Page 22 of 39

C9 1Reserved

CA 1RCAP2L Capture for Timer 2, auto-

reload, up-counter

D7 D6 D5 D4 D3 D2 D1 D0 00000000RW

CB 1RCAP2H Capture for Timer 2, auto-

reload, up-counter

D7 D6 D5 D4 D3 D2 D1 D0 00000000RW

CC 1TL2 Timer 2 reload L D7 D6 D5 D4 D3 D2 D1 D0 00000000RW

CD 1TH2 Timer 2 reload H D15 D14 D13 D12 D11 D10 D9 D8 00000000 RW

CE 2Reserved

D0 1PSW Program Status Word (bit

addressable)

CY AC F0 RS1 RS0 OV F1 P00000000RW

D1 7Reserved

D8 1EICON[12] External Interrupt Control SMOD1 1ERESI RESI INT6 0 0 0 01000000RW

D9 7Reserved

E0 1ACC Accumulator (bit address-

able)

D7 D6 D5 D4 D3 D2 D1 D0 00000000RW

E1 7Reserved

E8 1EIE[12] External Interrupt En-

able(s)

1 1 1 EX6 EX5 EX4 EI²C EUSB 11100000RW

E9 7Reserved

F0 1 B B (bit addressable) D7 D6 D5 D4 D3 D2 D1 D0 00000000RW

F1 7Reserved

F8 1EIP[12] External Interrupt Priority

Control

1 1 1 PX6 PX5 PX4 PI²C PUSB 11100000RW

F9 7Reserved

Table 5-1. FX2LP18 Register Summary (continued)

Hex SizeName Description b7 b6 b5 b4 b3 b2 b1 b0 Default Access

LedgendR = all bits read-onlyW = all bits write-onlyr = read-only bitw = write-only bitb = both read/write bit

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Contents

Main MoBL-USB FX2LP18 USB Microcontroller 1.0 CY7C68053 Features MoBL-USB FX2LP18 Block Diagram 2.0 Applications 3.0 Functional Overview 3.1 USB Signaling Speed 3.2 8051 Microprocessor CY7C68053 3.3 I2C Bus 3.4 Buses 3.5 USB Boot Methods 3.6 ReNumeration Page CY7C68053 3.9 Reset and Wakeup CY7C68053 3.10 Program/Data RAM 3.11 Register Addresses 3.12 Endpoint RAM Page CY7C68053 3.13 External FIFO Interface 3.14 GPIF 3.15 ECC Generation 3.16 USB Uploads and Downloads 3.17 Autopointer Access 3.18 I2C Controller 4.0 Pin Assignments Port GPIF Master Slave FIFO Figure 4-2. CY7C68053 56-pin VFBGA Pin Assignment - Top view 4.1 CY7C68053 Pin Descriptions Appropriate bulk/bypass capacitance should be provided for this Page Page Page 5.0 Register Summary Note 11. The register can only be reset, it cannot be set. Table 5-1. FX2LP18 Register Summary (continued) Page Document # 001-06120 Rev *F Page 20 of 39 Page Page 6.0 Absolute Maximum Ratings 7.0 Operating Conditions 8.0 DC Characteristics 9.0 AC Electrical Characteristics 9.1 USB Transceiver 9.2 GPIF Synchronous Signals 9.3 Slave FIFO Synchronous Read 9.4 Slave FIFO Asynchronous Read 9.5 Slave FIFO Synchronous Write 9.6 Slave FIFO Asynchronous Write 9.7 Slave FIFO Synchronous Packet End Strobe 9.8 Slave FIFO Asynchronous Packet End Strobe 9.9 Slave FIFO Output Enable 9.10 Slave FIFO Address to Flags/Data 9.11 Slave FIFO Synchronous Address 9.12 Slave FIFO Asynchronous Address 9.13 Sequence Diagram Page Page Page 10.0 Ordering Information 11.0 Package Diagram Table 10-1. Ordering Information Ordering Code Package Type RAM Size # Prog I/Os 12.0 PCB Layout Recommendations Document History Page