Cypress CY7C68053 manual AC Electrical Characteristics, USB Transceiver, Gpif Synchronous Signals

CY7C68053

9.0AC Electrical Characteristics

9.1USB Transceiver

USB 2.0-compliant in full- and high-speed modes.

9.2GPIF Synchronous Signals

Figure 9-1. GPIF Synchronous Signals Timing Diagram[17]

tIFCLK

IFCLK

t

GPIFADR[8:0]

RDYX
tSRY
	tRYH
DATA(input)	valid
tSGD	t
	DAH

CTLX

tXCTL

DATA(output)N

tXGD

N+1

Table 9-1. GPIF Synchronous Signals Parameters with Internally Sourced IFCLK[17,18]

Parameter	Description	Min.	Max.	Unit
tIFCLK	IFCLK Period	20.83		ns
tSRY	RDYX to Clock Set-up Time	8.9		ns
tRYH	Clock to RDYX	0		ns
tSGD	GPIF Data to Clock Set-up Time	9.2		ns
tDAH	GPIF Data Hold Time	0		ns
tXGD	Clock to GPIF Data Output Propagation Delay		11	ns
tXCTL	Clock to CTLX Output Propagation Delay		6.7	ns
8
Table 9-2. GPIF Synchronous Signals Parameters with Externally Sourced IFCLK[18]
Parameter	Description	Min.	Max.	Unit
tIFCLK	IFCLK Period[19]	20.83	200	ns
tSRY	RDYX to Clock Set-up Time	2.9		ns
tRYH	Clock to RDYX	3.7		ns
tSGD	GPIF Data to Clock Set-up Time	3.2		ns
tDAH	GPIF Data Hold Time	4.5		ns
tXGD	Clock to GPIF Data Output Propagation Delay		15	ns
tXCTL	Clock to CTLX Output Propagation Delay		13.06	ns

Notes

17.Dashed lines denote signals with programmable polarity.

18.GPIF asynchronous RDYx signals have a minimum set-up time of 50 ns when using internal 48 MHz IFCLK.

19.IFCLK must not exceed 48 MHz.

Document # 001-06120 Rev *F Page 25 of 39

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