Cypress manual CY7C68053 Features, Block Diagram, Cypress Semiconductor Corporation

CY7C68053

MoBL-USB™ FX2LP18 USB Microcontroller

1.0CY7C68053 Features

•USB 2.0 – USB-IF High-Speed and Full-Speed Compliant (TID# 40000188)

•Single-chip integrated USB 2.0 transceiver, smart SIE, and enhanced 8051 microprocessor

•Ideal for mobile applications (cell phone, smart phones, PDAs, MP3 players)

—Ultra low power

—Suspend current: 20 µA (typical)

•Software: 8051 code runs from:

—Internal RAM, which is loaded from EEPROM

•16 kBytes of on-chip Code/Data RAM

•Four programmable BULK/INTERRUPT/ISOCHRONOUS endpoints

—Buffering options: double, triple, and quad

•Additional programmable (BULK/INTERRUPT) 64-byte endpoint

•8- or 16-bit external data interface

•Smart Media Standard ECC generation

•GPIF (General Programmable Interface)

—Allows direct connection to most parallel interface

—Programmable waveform descriptors and configuration registers to define waveforms

—Supports multiple Ready (RDY) inputs and Control (CTL) outputs

•Integrated, industry standard enhanced 8051

—48 MHz, 24 MHz, or 12 MHz CPU operation

—Four clocks per instruction cycle

—Three counter/timers

—Expanded interrupt system

—Two data pointers

•1.8V core operation

•1.8V - 3.3V IO operation

•Vectored USB interrupts and GPIF/FIFO interrupts

•Separate data buffers for the Set-up and Data portions of a CONTROL transfer

•Integrated I2C™ controller, runs at 100 or 400 kHz

•Four integrated FIFO’s

—Integrated glue logic and FIFO’s lower system cost

—Automatic conversion to and from 16-bit buses

—Master or slave operation

—Uses external clock or asynchronous strobes

—Easy interface to ASIC and DSP IC’s

•Available in Industrial temperature grade

•Available in one lead-free package with up to 24 GPIO’s

—56-pin VFBGA (24 GPIO’s)

Block Diagram		High-performance micro
	24 MHz	using standard tools
	Ext. XTAL	with lower-power options

					MoBL-USB FX2LP18
	x20	/0.5		8051 Core		I2C
VCC		/1.0			(8)	Master
	PLL			12/24/48 MHz,
		/2.0			Bus
				Four Clocks/Cycle
1.5K						Additional I/Os (24)
					Data/
	Full-Speed
	Connected for
D+					( 16)
					ddressA	GPIF
D–	USB		Smart	RAM
						ECC
	2.0		CY	16 KB			RDY (2)
							CTL (3)
	XCVR		USB
Integrated			1.1/2.0
Full- and High-speed			Engine
XCVR						4 KB	8/16
						FIFO

Enhanced USB Core	“Soft Configuration”	FIFO and Endpoint Memory
Simplifies 8051 Code	Easy Firmware Changes	(master or slave operation)

Abundant I/O

General Programmable I/F

To Baseband processors/ Application processors/ ASICS/DSPs

Up to 96 MBytes/sec Burst Rate

Cypress Semiconductor Corporation	•	198 Champion Court • San Jose, CA 95134-1709	•	408-943-2600
Document # 001-06120 Rev *F		Revised September 9th 2006

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